From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 188ECA0613 for ; Fri, 30 Aug 2019 08:31:57 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 162DA1E570; Fri, 30 Aug 2019 08:31:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 649BB1BECA for ; Fri, 30 Aug 2019 08:31:54 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x7U6UO7W027743; Thu, 29 Aug 2019 23:31:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=WcDp0ILVcGPqiiIpPNNUtESSeTlcTgXPemgymQQEzj4=; b=lCzaSRqcOrolwGOBIejVBaNX/nyYc8bVSZqiEsk3gyRuSUU6NfgC4P0WatjHK8Vcbph5 DH6/cEKangKj5iPM7/jBt7VjMc2cMay1iYDa5rtEa103d/N5Uj109tXKCHAim3q7ZeNb M/iOywtQNIDKYR1wV0GhUAWVKkQ34UMyf2G3dn9MZvkgj1FCK0TMp+vJMmb48fP7Ngt3 bP1GAFUUgtUH2r2sk15OjESrmo8x48lBkVAA/oTln/ldwp+CNkGdaZDsrrzsf+lRnsQM jhHm4Yq4siQ2A9qwwQINmTqfgJ1s/yhbAMUABulVbskhzsyBZ5jUWpcmvZUsZYxc4emy cw== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg1m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2019 23:31:52 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 29 Aug 2019 23:31:50 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 29 Aug 2019 23:31:50 -0700 Received: from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56]) by maili.marvell.com (Postfix) with ESMTP id 2B0563F703F; Thu, 29 Aug 2019 23:31:46 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Pablo de Lara , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Narayana Prasad , Anoob Joseph , Tejasree Kondoj , Date: Fri, 30 Aug 2019 11:58:11 +0530 Message-ID: <1567146501-8224-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567146501-8224-1-git-send-email-anoobj@marvell.com> References: <1567146501-8224-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0 Subject: [dpdk-dev] [PATCH 01/11] crypto/octeontx2: add PMD skeleton X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi Adding OCTEON TX2 crypto PMD skeleton. Enabling the driver by default in common_base. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- config/common_base | 5 + drivers/common/Makefile | 5 +- drivers/crypto/Makefile | 1 + drivers/crypto/meson.build | 4 +- drivers/crypto/octeontx2/Makefile | 37 +++++++ drivers/crypto/octeontx2/meson.build | 29 +++++ drivers/crypto/octeontx2/otx2_cryptodev.c | 118 +++++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev.h | 25 +++++ drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 27 +++++ drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 12 +++ .../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 + mk/rte.app.mk | 6 +- 12 files changed, 269 insertions(+), 4 deletions(-) create mode 100644 drivers/crypto/octeontx2/Makefile create mode 100644 drivers/crypto/octeontx2/meson.build create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h create mode 100644 drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map diff --git a/config/common_base b/config/common_base index 8ef75c2..b8143ea 100644 --- a/config/common_base +++ b/config/common_base @@ -593,6 +593,11 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4 CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y # +# Compile PMD for Marvell OCTEON TX2 crypto device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y + +# # Compile PMD for QuickAssist based devices - see docs for details # CONFIG_RTE_LIBRTE_PMD_QAT=y diff --git a/drivers/common/Makefile b/drivers/common/Makefile index bc6f972..1ff033b 100644 --- a/drivers/common/Makefile +++ b/drivers/common/Makefile @@ -4,7 +4,9 @@ include $(RTE_SDK)/mk/rte.vars.mk -ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y) +CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) +CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) +ifneq (,$(findstring y,$(CPT-y))) DIRS-y += cpt endif @@ -12,6 +14,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO DIRS-y += octeontx endif OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) +OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) ifeq ($(findstring y,$(OCTEONTX2-y)),y) DIRS-y += octeontx2 endif diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 009f844..0ac999c 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx +DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += octeontx2 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index 83e7886..3c88f3c 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -2,8 +2,8 @@ # Copyright(c) 2017 Intel Corporation drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec', - 'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler', - 'snow3g', 'virtio', 'zuc'] + 'kasumi', 'mvsam', 'null', 'octeontx', 'octeontx2', 'openssl', 'qat', + 'scheduler', 'snow3g', 'virtio', 'zuc'] std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps config_flag_fmt = 'RTE_LIBRTE_@0@_PMD' diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile new file mode 100644 index 0000000..3273178 --- /dev/null +++ b/drivers/crypto/octeontx2/Makefile @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2019 Marvell International Ltd. +# + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_octeontx2_crypto.a + +# library version +LIBABIVER := 1 + +# build flags +CFLAGS += $(WERROR_FLAGS) + +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring +LDLIBS += -lrte_cryptodev +LDLIBS += -lrte_pci -lrte_bus_pci +LDLIBS += -lrte_common_cpt -lrte_common_octeontx2 + +VPATH += $(RTE_SDK)/drivers/crypto/octeontx2 + +CFLAGS += -O3 +CFLAGS += -I$(RTE_SDK)/drivers/common/cpt +CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2 + +# PMD code +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c + +# export include files +SYMLINK-y-include += + +# versioning export map +EXPORT_MAP := rte_pmd_octeontx2_crypto_version.map + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build new file mode 100644 index 0000000..2b55d2a --- /dev/null +++ b/drivers/crypto/octeontx2/meson.build @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2019 Marvell International Ltd. + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['bus_pci'] +deps += ['common_cpt'] +deps += ['common_octeontx2'] +name = 'octeontx2_crypto' + +sources = files('otx2_cryptodev.c', + 'otx2_cryptodev_ops.c') + +extra_flags = [] +# This integrated controller runs only on a arm64 machine, remove 32bit warnings +if not dpdk_conf.get('RTE_ARCH_64') + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast'] +endif + +foreach flag: extra_flags + if cc.has_argument(flag) + cflags += flag + endif +endforeach + +includes += include_directories('../../common/cpt') +includes += include_directories('../../common/octeontx2') diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c new file mode 100644 index 0000000..cf3a010 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* CPT common headers */ +#include "cpt_common.h" +#include "cpt_pmd_logs.h" + +#include "otx2_common.h" +#include "otx2_cryptodev.h" +#include "otx2_cryptodev_ops.h" + +static int otx2_cryptodev_logtype; + +static struct rte_pci_id pci_id_cpt_table[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, + PCI_DEVID_OCTEONTX2_RVU_CPT_VF) + }, + /* sentinel */ + { + .device_id = 0 + }, +}; + +static int +otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + struct rte_cryptodev_pmd_init_params init_params = { + .name = "", + .socket_id = rte_socket_id(), + .private_data_size = sizeof(struct otx2_cpt_vf) + }; + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + struct rte_cryptodev *dev; + int ret; + + /* Initialize logtype used in common */ + cpt_logtype = otx2_cryptodev_logtype; + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + dev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params); + if (dev == NULL) { + ret = -ENODEV; + goto exit; + } + + dev->dev_ops = &otx2_cpt_ops; + + dev->driver_id = otx2_cryptodev_driver_id; + + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED | + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | + RTE_CRYPTODEV_FF_IN_PLACE_SGL | + RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | + RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT; + + return 0; + +exit: + CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)", + pci_dev->id.vendor_id, pci_dev->id.device_id); + return ret; +} + +static int +otx2_cpt_pci_remove(struct rte_pci_device *pci_dev) +{ + char name[RTE_CRYPTODEV_NAME_MAX_LEN]; + struct rte_cryptodev *dev; + + if (pci_dev == NULL) + return -EINVAL; + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + dev = rte_cryptodev_pmd_get_named_dev(name); + if (dev == NULL) + return -ENODEV; + + return rte_cryptodev_pmd_destroy(dev); +} + +static struct rte_pci_driver otx2_cryptodev_pmd = { + .id_table = pci_id_cpt_table, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = otx2_cpt_pci_probe, + .remove = otx2_cpt_pci_remove, +}; + +static struct cryptodev_driver otx2_cryptodev_drv; + +RTE_INIT(otx2_cpt_init_log); +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table); +RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver, + otx2_cryptodev_driver_id); + +RTE_INIT(otx2_cpt_init_log) +{ + /* Bus level logs */ + otx2_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx2"); + if (otx2_cryptodev_logtype >= 0) + rte_log_set_level(otx2_cryptodev_logtype, RTE_LOG_NOTICE); +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h new file mode 100644 index 0000000..da0f653 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_H_ +#define _OTX2_CRYPTODEV_H_ + +#include "cpt_common.h" + +/* Marvell OCTEON TX2 Crypto PMD device name */ +#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2 + +/** + * Device private data + */ +struct otx2_cpt_vf { + /* To be populated */ +}; + +/* + * Crypto device driver ID + */ +uint8_t otx2_cryptodev_driver_id; + +#endif /* _OTX2_CRYPTODEV_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c new file mode 100644 index 0000000..18ad470 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#include + +#include "otx2_cryptodev_ops.h" + +struct rte_cryptodev_ops otx2_cpt_ops = { + /* Device control ops */ + .dev_configure = NULL, + .dev_start = NULL, + .dev_stop = NULL, + .dev_close = NULL, + .dev_infos_get = NULL, + + .stats_get = NULL, + .stats_reset = NULL, + .queue_pair_setup = NULL, + .queue_pair_release = NULL, + .queue_pair_count = NULL, + + /* Symmetric crypto ops */ + .sym_session_get_size = NULL, + .sym_session_configure = NULL, + .sym_session_clear = NULL, +}; diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h new file mode 100644 index 0000000..545614e --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2019 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_OPS_H_ +#define _OTX2_CRYPTODEV_OPS_H_ + +#include + +struct rte_cryptodev_ops otx2_cpt_ops; + +#endif /* _OTX2_CRYPTODEV_OPS_H_ */ diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map new file mode 100644 index 0000000..9a61188 --- /dev/null +++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map @@ -0,0 +1,4 @@ +DPDK_19.08 { + + local: *; +}; diff --git a/mk/rte.app.mk b/mk/rte.app.mk index ba5c39e..f85e50e 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -101,7 +101,9 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUX),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni endif -ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y) +OTX-CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) +OTX-CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) +ifeq ($(findstring y,$(OTX-CPT-y)),y) _LDLIBS-y += -lrte_common_cpt endif @@ -109,6 +111,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO _LDLIBS-y += -lrte_common_octeontx endif OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) +OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) @@ -268,6 +271,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -lrte_pmd_armv8 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += -lrte_pmd_octeontx2_crypto _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y) ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy) -- 2.7.4