From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C04BCA0613 for ; Thu, 26 Sep 2019 16:05:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 57DE51BEBD; Thu, 26 Sep 2019 16:05:11 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id EFB3A1BEA1 for ; Thu, 26 Sep 2019 16:04:55 +0200 (CEST) Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 9792FC2899D8931CB582; Thu, 26 Sep 2019 22:04:53 +0800 (CST) Received: from localhost.localdomain (10.67.212.132) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Thu, 26 Sep 2019 22:04:42 +0800 From: "Wei Hu (Xavier)" To: CC: , , , Date: Thu, 26 Sep 2019 22:01:48 +0800 Message-ID: <1569506528-60464-3-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569506528-60464-1-git-send-email-xavier.huwei@huawei.com> References: <1569506528-60464-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.132] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v3 02/22] net/hns3: add hardware registers definition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds hardware definition header file for hns3 PMD driver. Signed-off-by: Wei Hu (Xavier) Signed-off-by: Chunsong Feng Signed-off-by: Min Hu (Connor) Signed-off-by: Hao Chen Signed-off-by: Huisong Li --- drivers/net/hns3/hns3_regs.h | 98 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 drivers/net/hns3/hns3_regs.h diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h new file mode 100644 index 0000000..5a4f315 --- /dev/null +++ b/drivers/net/hns3/hns3_regs.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2019 Hisilicon Limited. + */ + +#ifndef _HNS3_REGS_H_ +#define _HNS3_REGS_H_ + +/* bar registers for cmdq */ +#define HNS3_CMDQ_TX_ADDR_L_REG 0x27000 +#define HNS3_CMDQ_TX_ADDR_H_REG 0x27004 +#define HNS3_CMDQ_TX_DEPTH_REG 0x27008 +#define HNS3_CMDQ_TX_TAIL_REG 0x27010 +#define HNS3_CMDQ_TX_HEAD_REG 0x27014 +#define HNS3_CMDQ_RX_ADDR_L_REG 0x27018 +#define HNS3_CMDQ_RX_ADDR_H_REG 0x2701c +#define HNS3_CMDQ_RX_DEPTH_REG 0x27020 +#define HNS3_CMDQ_RX_TAIL_REG 0x27024 +#define HNS3_CMDQ_RX_HEAD_REG 0x27028 +#define HNS3_CMDQ_INTR_STS_REG 0x27104 +#define HNS3_CMDQ_INTR_EN_REG 0x27108 +#define HNS3_CMDQ_INTR_GEN_REG 0x2710C + +/* Vector0 interrupt CMDQ event source register(RW) */ +#define HNS3_VECTOR0_CMDQ_SRC_REG 0x27100 +/* Vector0 interrupt CMDQ event status register(RO) */ +#define HNS3_VECTOR0_CMDQ_STAT_REG 0x27104 + +#define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800 + +#define HNS3_MISC_VECTOR_REG_BASE 0x20400 +#define HNS3_VECTOR0_OTER_EN_REG 0x20600 +#define HNS3_MISC_RESET_STS_REG 0x20700 +#define HNS3_GLOBAL_RESET_REG 0x20A00 +#define HNS3_FUN_RST_ING 0x20C00 +#define HNS3_GRO_EN_REG 0x28000 + +/* Vector0 register bits for reset */ +#define HNS3_VECTOR0_FUNCRESET_INT_B 0 +#define HNS3_VECTOR0_GLOBALRESET_INT_B 5 +#define HNS3_VECTOR0_CORERESET_INT_B 6 +#define HNS3_VECTOR0_IMPRESET_INT_B 7 + +/* CMDQ register bits for RX event(=MBX event) */ +#define HNS3_VECTOR0_RX_CMDQ_INT_B 1 +#define HNS3_VECTOR0_REG_MSIX_MASK 0x1FF00 +/* RST register bits for RESET event */ +#define HNS3_VECTOR0_RST_INT_B 2 + +#define HNS3_VF_RST_ING 0x07008 +#define HNS3_VF_RST_ING_BIT BIT(16) + +/* bar registers for rcb */ +#define HNS3_RING_RX_BASEADDR_L_REG 0x00000 +#define HNS3_RING_RX_BASEADDR_H_REG 0x00004 +#define HNS3_RING_RX_BD_NUM_REG 0x00008 +#define HNS3_RING_RX_BD_LEN_REG 0x0000C +#define HNS3_RING_RX_MERGE_EN_REG 0x00014 +#define HNS3_RING_RX_TAIL_REG 0x00018 +#define HNS3_RING_RX_HEAD_REG 0x0001C +#define HNS3_RING_RX_FBDNUM_REG 0x00020 +#define HNS3_RING_RX_OFFSET_REG 0x00024 +#define HNS3_RING_RX_FBD_OFFSET_REG 0x00028 +#define HNS3_RING_RX_PKTNUM_RECORD_REG 0x0002C +#define HNS3_RING_RX_STASH_REG 0x00030 +#define HNS3_RING_RX_BD_ERR_REG 0x00034 + +#define HNS3_RING_TX_BASEADDR_L_REG 0x00040 +#define HNS3_RING_TX_BASEADDR_H_REG 0x00044 +#define HNS3_RING_TX_BD_NUM_REG 0x00048 +#define HNS3_RING_TX_PRIORITY_REG 0x0004C +#define HNS3_RING_TX_TC_REG 0x00050 +#define HNS3_RING_TX_MERGE_EN_REG 0x00054 +#define HNS3_RING_TX_TAIL_REG 0x00058 +#define HNS3_RING_TX_HEAD_REG 0x0005C +#define HNS3_RING_TX_FBDNUM_REG 0x00060 +#define HNS3_RING_TX_OFFSET_REG 0x00064 +#define HNS3_RING_TX_EBD_NUM_REG 0x00068 +#define HNS3_RING_TX_PKTNUM_RECORD_REG 0x0006C +#define HNS3_RING_TX_EBD_OFFSET_REG 0x00070 +#define HNS3_RING_TX_BD_ERR_REG 0x00074 + +#define HNS3_RING_EN_REG 0x00090 + +#define HNS3_RING_EN_B 0 + +#define HNS3_TQP_REG_OFFSET 0x80000 +#define HNS3_TQP_REG_SIZE 0x200 + +/* bar registers for tqp interrupt */ +#define HNS3_TQP_INTR_CTRL_REG 0x20000 +#define HNS3_TQP_INTR_GL0_REG 0x20100 +#define HNS3_TQP_INTR_GL1_REG 0x20200 +#define HNS3_TQP_INTR_GL2_REG 0x20300 +#define HNS3_TQP_INTR_RL_REG 0x20900 + +#define HNS3_TQP_INTR_REG_SIZE 4 + +#endif /* _HNS3_REGS_H_ */ -- 2.7.4