From: Nicolas Chautru <nicolas.chautru@intel.com>
To: akhil.goyal@nxp.com, dev@dpdk.org
Cc: ferruh.yigit@intel.com, thomas@monjalon.net,
Nic Chautru <nicolas.chautru@intel.com>
Subject: [dpdk-dev] [PATCH v1 2/2] baseband/fpga_lte_fec: fix to polling of MMIO register
Date: Mon, 21 Oct 2019 12:24:10 -0700 [thread overview]
Message-ID: <1571685850-382423-3-git-send-email-nicolas.chautru@intel.com> (raw)
In-Reply-To: <1571685850-382423-1-git-send-email-nicolas.chautru@intel.com>
From: Nic Chautru <nicolas.chautru@intel.com>
Polling of a MMIO register could misreport the actual value
set dynamically in hardware as the variable was not set explictly to
volatile integer.
Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c
index 2fc7f11..8bd10b4 100644
--- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c
+++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c
@@ -889,7 +889,7 @@ struct __rte_cache_aligned fpga_queue {
* completed. If completion flag is not updated within 1ms it is
* considered as a failure.
*/
- while (!(*((uint8_t *)d->flush_queue_status + q->q_idx) & payload)) {
+ while (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx) & payload)) {
if (counter > timeout) {
rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d",
queue_id);
--
1.8.3.1
next prev parent reply other threads:[~2019-10-22 2:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-21 19:24 [dpdk-dev] [PATCH v1 0/2] baseband/fpga_lte_fec: bug fixes from HW validation Nicolas Chautru
2019-10-21 19:24 ` [dpdk-dev] [PATCH v1 1/2] baseband/fpga_lte_fec: fix probing fatal failure Nicolas Chautru
2019-10-21 19:24 ` Nicolas Chautru [this message]
2019-10-22 7:58 ` [dpdk-dev] [PATCH v1 0/2] baseband/fpga_lte_fec: bug fixes from HW validation Akhil Goyal
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