From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from dpdk.org (dpdk.org [92.243.14.124])
by inbox.dpdk.org (Postfix) with ESMTP id 53E0DA0524;
Fri, 31 Jan 2020 11:06:41 +0100 (CET)
Received: from [92.243.14.124] (localhost [127.0.0.1])
by dpdk.org (Postfix) with ESMTP id 4769F1C18F;
Fri, 31 Jan 2020 11:05:25 +0100 (CET)
Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com
[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 74A9B1C139
for <dev@dpdk.org>; Fri, 31 Jan 2020 11:05:23 +0100 (CET)
Received: from pps.filterd (m0045849.ppops.net [127.0.0.1])
by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id
00VA06vN014004; Fri, 31 Jan 2020 02:05:22 -0800
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;
h=from : to : cc :
subject : date : message-id : in-reply-to : references : mime-version :
content-transfer-encoding : content-type; s=pfpt0818;
bh=XRnqlEx7alZtWBupqfgrNiY3iNsy3kzzPlF9ccUnmAQ=;
b=lhI4zzEHRQJFMTjKCNaVPZvKA+mfDoXYSzh9H7TAyi2MmuZC9H7LTX3LNwuXbataZQr0
1Ol06qROMXKhLp2TOHXxx+NXDVOYzjps2yctXicZLCRCF6xDZD+9U/8l7W/MLomy45Pm
NXDPIhebqsXtodkHtjPv5CgKJ3Zj6qXxprC2IxOh5kU+FnmEj2mxSHXF6wQX5o7PzDty
Wem5HeS75kX6/mXw3+z0Wqj9BkFsQESTkU1t7x7Q46fYQ2MXcsd6GgC5zTT/TUSqPhNY
/WzmPb9g6VQrLCG3cUhbSnxCKOhhacy0C4mzs5agmK1PAUN+FOxj0lzenvXPAJuQACzB Lg==
Received: from sc-exch04.marvell.com ([199.233.58.184])
by mx0a-0016f401.pphosted.com with ESMTP id 2xupkhxx5a-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);
Fri, 31 Jan 2020 02:05:22 -0800
Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com
(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 31 Jan
2020 02:05:21 -0800
Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com
(10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend
Transport; Fri, 31 Jan 2020 02:05:21 -0800
Received: from ajoseph83.caveonetworks.com (unknown [10.29.45.60])
by maili.marvell.com (Postfix) with ESMTP id CF0F53F7043;
Fri, 31 Jan 2020 02:05:16 -0800 (PST)
From: Anoob Joseph <anoobj@marvell.com>
To: Akhil Goyal <akhil.goyal@nxp.com>, Declan Doherty
<declan.doherty@intel.com>, Thomas Monjalon <thomas@monjalon.net>
CC: Tejasree Kondoj <ktejasree@marvell.com>, Jerin Jacob <jerinj@marvell.com>,
Narayana Prasad <pathreya@marvell.com>, Kiran Kumar K
<kirankumark@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
"Pavan Nikhilesh" <pbhagavatula@marvell.com>, Ankur Dwivedi
<adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,
Archana Muniganti <marchana@marvell.com>,
Vamsi Attunuru <vattunuru@marvell.com>, Lukasz
Bartosik <lbartosik@marvell.com>, <dev@dpdk.org>
Date: Fri, 31 Jan 2020 15:33:51 +0530
Message-ID: <1580465035-30455-12-git-send-email-anoobj@marvell.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1580465035-30455-1-git-send-email-anoobj@marvell.com>
References: <1579344553-11428-1-git-send-email-anoobj@marvell.com>
<1580465035-30455-1-git-send-email-anoobj@marvell.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572
definitions=2020-01-31_02:2020-01-30,
2020-01-31 signatures=0
Subject: [dpdk-dev] [PATCH v3 11/15] net/octeontx2: add inline ipsec Rx path
changes
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
From: Tejasree Kondoj <ktejasree@marvell.com>
Adding post-processing required for inline IPsec inbound packets.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
---
drivers/crypto/octeontx2/Makefile | 3 +-
drivers/crypto/octeontx2/meson.build | 2 +
drivers/event/octeontx2/Makefile | 1 +
drivers/event/octeontx2/meson.build | 2 +
drivers/net/octeontx2/otx2_rx.h | 73 ++++++++++++++++++++++++++++++++++++
5 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 3ba67ed..1458e2b 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -11,7 +11,7 @@ LIB = librte_pmd_octeontx2_crypto.a
CFLAGS += $(WERROR_FLAGS)
LDLIBS += -lrte_eal -lrte_ethdev -lrte_mbuf -lrte_mempool -lrte_ring
-LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_cryptodev -lrte_security
LDLIBS += -lrte_pci -lrte_bus_pci
LDLIBS += -lrte_common_cpt -lrte_common_octeontx2
@@ -20,6 +20,7 @@ VPATH += $(RTE_SDK)/drivers/crypto/octeontx2
CFLAGS += -O3
CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/crypto/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2
CFLAGS += -DALLOW_EXPERIMENTAL_API
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index 67deca3..a531799 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -9,6 +9,7 @@ deps += ['bus_pci']
deps += ['common_cpt']
deps += ['common_octeontx2']
deps += ['ethdev']
+deps += ['security']
name = 'octeontx2_crypto'
allow_experimental_apis = true
@@ -32,5 +33,6 @@ endforeach
includes += include_directories('../../common/cpt')
includes += include_directories('../../common/octeontx2')
+includes += include_directories('../../crypto/octeontx2')
includes += include_directories('../../mempool/octeontx2')
includes += include_directories('../../net/octeontx2')
diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile
index 6dab69c..bcd22ee 100644
--- a/drivers/event/octeontx2/Makefile
+++ b/drivers/event/octeontx2/Makefile
@@ -11,6 +11,7 @@ LIB = librte_pmd_octeontx2_event.a
CFLAGS += $(WERROR_FLAGS)
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/crypto/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/event/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2
diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build
index 807818b..56febb8 100644
--- a/drivers/event/octeontx2/meson.build
+++ b/drivers/event/octeontx2/meson.build
@@ -32,3 +32,5 @@ foreach flag: extra_flags
endforeach
deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2']
+
+includes += include_directories('../../crypto/octeontx2')
diff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h
index 351ad0f..eac4717 100644
--- a/drivers/net/octeontx2/otx2_rx.h
+++ b/drivers/net/octeontx2/otx2_rx.h
@@ -5,6 +5,12 @@
#ifndef __OTX2_RX_H__
#define __OTX2_RX_H__
+#include <rte_ether.h>
+
+#include "otx2_common.h"
+#include "otx2_ethdev_sec.h"
+#include "otx2_ipsec_fp.h"
+
/* Default mark value used when none is provided. */
#define OTX2_FLOW_ACTION_FLAG_DEFAULT 0xffff
@@ -31,6 +37,12 @@
#define NIX_RX_MULTI_SEG_F BIT(15)
#define NIX_TIMESYNC_RX_OFFSET 8
+/* Inline IPsec offsets */
+
+#define INLINE_INB_RPTR_HDR 16
+/* nix_cqe_hdr_s + nix_rx_parse_s + nix_rx_sg_s + nix_iova_s */
+#define INLINE_CPT_RESULT_OFFSET 80
+
struct otx2_timesync_info {
uint64_t rx_tstamp;
rte_iova_t tx_tstamp_iova;
@@ -190,6 +202,60 @@ nix_cqe_xtract_mseg(const struct nix_rx_parse_s *rx,
}
}
+static __rte_always_inline uint16_t
+nix_rx_sec_cptres_get(const void *cq)
+{
+ volatile const struct otx2_cpt_res *res;
+
+ res = (volatile const struct otx2_cpt_res *)((const char *)cq +
+ INLINE_CPT_RESULT_OFFSET);
+
+ return res->u16[0];
+}
+
+static __rte_always_inline void *
+nix_rx_sec_sa_get(const void * const lookup_mem, int spi, uint16_t port)
+{
+ const uint64_t *const *sa_tbl = (const uint64_t * const *)
+ ((const uint8_t *)lookup_mem + OTX2_NIX_SA_TBL_START);
+
+ return (void *)sa_tbl[port][spi];
+}
+
+static __rte_always_inline uint64_t
+nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m,
+ const void * const lookup_mem)
+{
+ struct otx2_ipsec_fp_in_sa *sa;
+ struct rte_ipv4_hdr *ipv4;
+ uint16_t m_len;
+ uint32_t spi;
+ char *data;
+
+ if (unlikely(nix_rx_sec_cptres_get(cq) != OTX2_SEC_COMP_GOOD))
+ return PKT_RX_SEC_OFFLOAD | PKT_RX_SEC_OFFLOAD_FAILED;
+
+ /* 20 bits of tag would have the SPI */
+ spi = cq->tag & 0xFFFFF;
+
+ sa = nix_rx_sec_sa_get(lookup_mem, spi, m->port);
+ m->udata64 = (uint64_t)sa->userdata;
+
+ data = rte_pktmbuf_mtod(m, char *);
+ memcpy(data + INLINE_INB_RPTR_HDR, data, RTE_ETHER_HDR_LEN);
+
+ m->data_off += INLINE_INB_RPTR_HDR;
+
+ ipv4 = (struct rte_ipv4_hdr *)(data + INLINE_INB_RPTR_HDR +
+ RTE_ETHER_HDR_LEN);
+
+ m_len = rte_be_to_cpu_16(ipv4->total_length) + RTE_ETHER_HDR_LEN;
+
+ m->data_len = m_len;
+ m->pkt_len = m_len;
+ return PKT_RX_SEC_OFFLOAD;
+}
+
static __rte_always_inline void
otx2_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
struct rte_mbuf *mbuf, const void *lookup_mem,
@@ -231,6 +297,13 @@ otx2_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
if (flag & NIX_RX_OFFLOAD_MARK_UPDATE_F)
ol_flags = nix_update_match_id(rx->match_id, ol_flags, mbuf);
+ if (cq->cqe_type == NIX_XQE_TYPE_RX_IPSECH) {
+ *(uint64_t *)(&mbuf->rearm_data) = val;
+ ol_flags |= nix_rx_sec_mbuf_update(cq, mbuf, lookup_mem);
+ mbuf->ol_flags = ol_flags;
+ return;
+ }
+
mbuf->ol_flags = ol_flags;
*(uint64_t *)(&mbuf->rearm_data) = val;
mbuf->pkt_len = len;
--
2.7.4