From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 69AE9A0559; Mon, 16 Mar 2020 10:36:01 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 746E41C0D4; Mon, 16 Mar 2020 10:35:03 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 83F011C0B7 for ; Mon, 16 Mar 2020 10:34:57 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 02G9UM5p015013; Mon, 16 Mar 2020 02:34:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-type : mime-version; s=pfpt0818; bh=4Fcv5N7zfkBWXFdTLetPomLoImbyGJRGDHwKUpj+6k4=; b=Xji1uJnFPOBqXRToj9COflT+qAtB9oGXZm/F+K1+P6x5Tcr8c4HoExjq2ote+Rqsn7H3 /Vi1nUNHN2Wefk8iabMq1PnIEecEbr5EXd8kAFCSVSK0eMVHppZHTQEfKWlo7RCeEmkv 7tY2/Of3qPG5x/XN8CLcBQQCBy0U//R5ULhwBkk2eGzFpmekuLFg+fXyhWOjW4uBWnk4 8j9UNPkXON0peMCLME4OKla/06TPEsaeZnfY4vRjBYCjdMwrLFk/MafoSXy31/EXhCI0 c3q03bdaXA8/9aeTgQddAY3MRGV8jX1A1v2Arn8acSYLoo3tZ0KYFZgq7wSp93BBRgDZ MA== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2yrxsme52k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 16 Mar 2020 02:34:56 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 16 Mar 2020 02:34:54 -0700 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.169) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2 via Frontend Transport; Mon, 16 Mar 2020 02:34:54 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WN70HYf9cn8z/D0BmsoQckxR+lMuqo7QZtGTSbvshsllw2XW/1BbahBVyWN7FPrW7p1yrg9JMIshOU2aqwww2SIrPEKD8J6ee80rRHuDg7l7DrGFfnWjbzPW8op0I6ofku1PyygTDRDc5aZgzfutuFMnqOc571nKj6Hb4YSf8+lGdagtLtPMRQGWOqobiTGH2WZBpH1ntjXyHMwBvBaPhflYP9ELpVWDrlt8njXUigczpxRMlibxtEd7l7nKrcmabwMNa8EhyhgDdIoiW9ZUUOkJ+4QsUtlxMEnuPZ+kSyzJPpSqM9tIW0rsPkR+4HLAbWOCPDaCiQYZS3R8oslrVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4Fcv5N7zfkBWXFdTLetPomLoImbyGJRGDHwKUpj+6k4=; b=KAroWTDn5NdzFdxRbkT36oW79MXw+q/uWzNcS0lyzgPj1HylGRBcRCwmyVYei0L86oTPNoFd483k9U8+FDbiP0FrJKCcuB1NBNeQP/LpA9twz5o8q+YSRUNixDTVjLe4LGQx/PLjIb5rl8DUzj/6ZRdq9LQ1A2gx/0Jmcca8zmwIPYWLRloPvPNK4G3DaXLrKxClqx9DbfBnOUenzxWeCnlEUysbVt7tilTJm93z0F8aGMRUhGLBEfT4PBNI2G79zeT44Xvj9tev0Qcf/CnIndj+GWy/ZCcL4YngNUaN6CjAu4ogiExYmJ03zjTd4fW6YLf/TnMyXvAZJtbEqbIc7A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com; dkim=pass header.d=marvell.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector1-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4Fcv5N7zfkBWXFdTLetPomLoImbyGJRGDHwKUpj+6k4=; b=g4AkzOUtB6cMnM069yc3CPMh+8OaehcznDg88zQwzjyyaMgIDLOz21F+shr2ge7+iXbjHYZsSn4RkKM6I5JEYsZs19EywP7cR+YAGQZlPu58KC66YuYQsCHtK82LNqcNlTAsV1MtH76dRH0pAF5OLeTu7Y/Or0x3uAVc4Uy6cag= Received: from MN2PR18MB2848.namprd18.prod.outlook.com (2603:10b6:208:38::19) by MN2PR18MB3117.namprd18.prod.outlook.com (2603:10b6:208:162::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2814.14; Mon, 16 Mar 2020 09:34:50 +0000 Received: from MN2PR18MB2848.namprd18.prod.outlook.com ([fe80::f829:3e55:94f6:4efb]) by MN2PR18MB2848.namprd18.prod.outlook.com ([fe80::f829:3e55:94f6:4efb%5]) with mapi id 15.20.2814.021; Mon, 16 Mar 2020 09:34:50 +0000 From: Harman Kalra To: , , CC: , Date: Mon, 16 Mar 2020 15:03:43 +0530 Message-ID: <1584351224-23500-8-git-send-email-hkalra@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584351224-23500-1-git-send-email-hkalra@marvell.com> References: <1584351224-23500-1-git-send-email-hkalra@marvell.com> Content-Type: text/plain X-ClientProxiedBy: BMXPR01CA0006.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::16) To MN2PR18MB2848.namprd18.prod.outlook.com (2603:10b6:208:38::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from hkarlara-OptiPlex-3046.marvell.com (115.113.156.2) by BMXPR01CA0006.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2814.13 via Frontend Transport; Mon, 16 Mar 2020 09:34:42 +0000 X-Mailer: git-send-email 2.7.4 X-Originating-IP: [115.113.156.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: abfcf5ad-ac55-4872-fce5-08d7c98d4275 X-MS-TrafficTypeDiagnostic: MN2PR18MB3117: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-Forefront-PRVS: 03449D5DD1 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(366004)(136003)(376002)(39860400002)(346002)(396003)(199004)(52116002)(7696005)(478600001)(4326008)(8676002)(8936002)(107886003)(26005)(66556008)(30864003)(2906002)(86362001)(5660300002)(36756003)(55236004)(16526019)(2616005)(956004)(66946007)(6486002)(66476007)(81156014)(81166006)(186003)(316002); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB3117; H:MN2PR18MB2848.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; Received-SPF: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iVNbsynzroWVciQhzux24bdzp+INSDg3ZiRl372wrKQyHuxdfznJqGnT9fxaqGaQA+DH/Qqf0ka7fiCip/I9tYLGunKgeT60wiCYpMFqtY+yCcF+hNvkgUgd7gfaqDB8Cn2QHbRGwWcRQ4pedKSH/y0mHdy0vQW6H1gxCxqGe0zTtV7Zns2Tpg8E6Xb6dwG9Uns0cR63OB+Iy3Fmro41vvDsi3+I0+Le9xdbdEM20Wobb5r9Pp7oPxvvBabRbh+E2pS+XHAAlsNjw4oU7f31wZW9xNExUMykO2GuqLyvvmUaPDcD8zmETVwyECVUXJfJxXNDBM95Tad06jW6V+mMyNzrUJcp2yNdmp+UA7u7iZ+9pr3qwpSGQIzMwf6Pg16npqOvUGKEKjyOC9kjy09LTSVJlRe1daEmupUuobaCd16vbbxlgWLi83qZVGpr8Ol1 X-MS-Exchange-AntiSpam-MessageData: rEFjQ445fkXY1GsoJ33sy7UKayWpTsbzokIXZBGqgjbU/+A21PbjsqGul8gD7F845lzr44cUbBf/dT3RvD6YDjknOILe/bdwja8uq+y7ThWPhC0qv7swEq4fUtZ1zX61O8MNJLg3mXBbBcfP7AfxYA== X-MS-Exchange-CrossTenant-Network-Message-Id: abfcf5ad-ac55-4872-fce5-08d7c98d4275 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2020 09:34:44.0424 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3FP7KP2ootXW7ggfgVgajOdvamOu3DyhcLvnu8DxA6Djqkt+5tfK7gmuE2YupM2MfCZA+AiAjR3q6sPCl2Cvqg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3117 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-03-16_02:2020-03-12, 2020-03-16 signatures=0 Subject: [dpdk-dev] [PATCH 7/8] net/octeontx: add flow control support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vamsi Attunuru Patch adds ethdev flow control set/get callback ops, pmd enables modifying flow control attributes like rx_pause, tx_pause, high & low water mark. Signed-off-by: Vamsi Attunuru --- doc/guides/nics/features/octeontx.ini | 1 + drivers/net/octeontx/base/octeontx_bgx.c | 50 ++++++++ drivers/net/octeontx/base/octeontx_bgx.h | 28 +++++ drivers/net/octeontx/octeontx_ethdev.c | 20 ++++ drivers/net/octeontx/octeontx_ethdev.h | 19 +++ drivers/net/octeontx/octeontx_ethdev_ops.c | 128 +++++++++++++++++++++ 6 files changed, 246 insertions(+) diff --git a/doc/guides/nics/features/octeontx.ini b/doc/guides/nics/features/octeontx.ini index 377bb4d30..6049c1c43 100644 --- a/doc/guides/nics/features/octeontx.ini +++ b/doc/guides/nics/features/octeontx.ini @@ -18,6 +18,7 @@ VLAN filter = Y VLAN offload = P CRC offload = Y Packet type parsing = Y +Flow control = Y Basic stats = Y Linux VFIO = Y ARMv8 = Y diff --git a/drivers/net/octeontx/base/octeontx_bgx.c b/drivers/net/octeontx/base/octeontx_bgx.c index d8611cb77..ac856ff86 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.c +++ b/drivers/net/octeontx/base/octeontx_bgx.c @@ -326,3 +326,53 @@ octeontx_bgx_port_mac_entries_get(int port) return resp; } + +int octeontx_bgx_port_get_fifo_cfg(int port, + octeontx_mbox_bgx_port_fifo_cfg_t *cfg) +{ + int len = sizeof(octeontx_mbox_bgx_port_fifo_cfg_t); + octeontx_mbox_bgx_port_fifo_cfg_t conf; + struct octeontx_mbox_hdr hdr; + + hdr.coproc = OCTEONTX_BGX_COPROC; + hdr.msg = MBOX_BGX_PORT_GET_FIFO_CFG; + hdr.vfid = port; + + if (octeontx_mbox_send(&hdr, NULL, 0, &conf, len) < 0) + return -EACCES; + + cfg->rx_fifosz = conf.rx_fifosz; + + return 0; +} + +int octeontx_bgx_port_flow_ctrl_cfg(int port, + octeontx_mbox_bgx_port_fc_cfg_t *cfg) +{ + int len = sizeof(octeontx_mbox_bgx_port_fc_cfg_t); + octeontx_mbox_bgx_port_fc_cfg_t conf; + struct octeontx_mbox_hdr hdr; + + hdr.coproc = OCTEONTX_BGX_COPROC; + hdr.msg = MBOX_BGX_PORT_FLOW_CTRL_CFG; + hdr.vfid = port; + + if (cfg->fc_cfg == BGX_PORT_FC_CFG_SET) + memcpy(&conf, cfg, len); + else + memset(&conf, 0, len); + + if (octeontx_mbox_send(&hdr, &conf, len, &conf, len) < 0) + return -EACCES; + + if (cfg->fc_cfg == BGX_PORT_FC_CFG_SET) + goto done; + + cfg->rx_pause = conf.rx_pause; + cfg->tx_pause = conf.tx_pause; + cfg->low_water = conf.low_water; + cfg->high_water = conf.high_water; + +done: + return 0; +} diff --git a/drivers/net/octeontx/base/octeontx_bgx.h b/drivers/net/octeontx/base/octeontx_bgx.h index 6b7476510..d126a0b7f 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.h +++ b/drivers/net/octeontx/base/octeontx_bgx.h @@ -11,6 +11,8 @@ #include +#define OCTEONTX_BGX_RSVD_RX_FIFOBYTES 0x40 + #define OCTEONTX_BGX_COPROC 6 /* BGX messages */ @@ -32,6 +34,8 @@ #define MBOX_BGX_PORT_ADD_MACADDR 15 #define MBOX_BGX_PORT_DEL_MACADDR 16 #define MBOX_BGX_PORT_GET_MACADDR_ENTRIES 17 +#define MBOX_BGX_PORT_GET_FIFO_CFG 18 +#define MBOX_BGX_PORT_FLOW_CTRL_CFG 19 #define MBOX_BGX_PORT_SET_LINK_STATE 20 /* BGX port configuration parameters: */ @@ -119,6 +123,26 @@ struct octeontx_mbox_bgx_port_mac_filter { int index; }; +/* BGX port fifo config: */ +typedef struct octeontx_mbox_bgx_port_fifo_cfg { + uint32_t rx_fifosz; /* in Bytes */ +} octeontx_mbox_bgx_port_fifo_cfg_t; + +typedef enum { + BGX_PORT_FC_CFG_GET = 0, + BGX_PORT_FC_CFG_SET = 1 +} bgx_port_fc_t; + +/* BGX port flow control config: */ +typedef struct octeontx_mbox_bgx_port_fc_cfg { + /* BP on/off threshold levels in Bytes, must be a multiple of 16 */ + uint16_t high_water; + uint16_t low_water; + uint8_t rx_pause; /* rx_pause = 1/0 to enable/disable fc on Tx */ + uint8_t tx_pause; /* tx_pause = 1/0 to enable/disable fc on Rx */ + bgx_port_fc_t fc_cfg; +} octeontx_mbox_bgx_port_fc_cfg_t; + int octeontx_bgx_port_open(int port, octeontx_mbox_bgx_port_conf_t *conf); int octeontx_bgx_port_close(int port); int octeontx_bgx_port_start(int port); @@ -135,6 +159,10 @@ int octeontx_bgx_port_mac_del(int port, uint32_t index); int octeontx_bgx_port_mac_entries_get(int port); int octeontx_bgx_port_mtu_set(int port, int mtu); int octeontx_bgx_port_set_link_state(int port, bool en); +int octeontx_bgx_port_get_fifo_cfg(int port, + octeontx_mbox_bgx_port_fifo_cfg_t *cfg); +int octeontx_bgx_port_flow_ctrl_cfg(int port, + octeontx_mbox_bgx_port_fc_cfg_t *cfg); #endif /* __OCTEONTX_BGX_H__ */ diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index 08c621b4b..191869683 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -122,6 +122,7 @@ static int octeontx_port_open(struct octeontx_nic *nic) { octeontx_mbox_bgx_port_conf_t bgx_port_conf; + octeontx_mbox_bgx_port_fifo_cfg_t fifo_cfg; int res; res = 0; @@ -147,6 +148,16 @@ octeontx_port_open(struct octeontx_nic *nic) nic->mcast_mode = bgx_port_conf.mcast_mode; nic->speed = bgx_port_conf.mode; + memset(&fifo_cfg, 0x0, sizeof(fifo_cfg)); + + res = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg); + if (res < 0) { + octeontx_log_err("failed to get port %d fifo cfg", res); + return res; + } + + nic->fc.rx_fifosz = fifo_cfg.rx_fifosz; + memcpy(&nic->mac_addr[0], &bgx_port_conf.macaddr[0], RTE_ETHER_ADDR_LEN); @@ -482,6 +493,8 @@ octeontx_dev_close(struct rte_eth_dev *dev) rte_event_dev_close(nic->evdev); + octeontx_dev_flow_ctrl_fini(dev); + octeontx_dev_vlan_offload_fini(dev); ret = octeontx_pko_channel_close(nic->base_ochan); @@ -1208,6 +1221,7 @@ octeontx_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, octeontx_recheck_rx_offloads(rxq); dev->data->rx_queues[qidx] = rxq; dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; + return 0; } @@ -1276,6 +1290,8 @@ static const struct eth_dev_ops octeontx_dev_ops = { .dev_supported_ptypes_get = octeontx_dev_supported_ptypes_get, .mtu_set = octeontx_dev_mtu_set, .pool_ops_supported = octeontx_pool_ops, + .flow_ctrl_get = octeontx_dev_flow_ctrl_get, + .flow_ctrl_set = octeontx_dev_flow_ctrl_set, }; /* Create Ethdev interface per BGX LMAC ports */ @@ -1407,6 +1423,10 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev, /* Update same mac address to BGX CAM table at index 0 */ octeontx_bgx_port_mac_add(nic->port_id, nic->mac_addr, 0); + res = octeontx_dev_flow_ctrl_init(eth_dev); + if (res < 0) + goto err; + PMD_INIT_LOG(DEBUG, "ethdev info: "); PMD_INIT_LOG(DEBUG, "port %d, port_ena %d ochan %d num_ochan %d tx_q %d", nic->port_id, nic->port_ena, diff --git a/drivers/net/octeontx/octeontx_ethdev.h b/drivers/net/octeontx/octeontx_ethdev.h index 186a044f7..dc53b53be 100644 --- a/drivers/net/octeontx/octeontx_ethdev.h +++ b/drivers/net/octeontx/octeontx_ethdev.h @@ -83,6 +83,16 @@ struct octeontx_vlan_info { uint8_t filter_on; }; +struct octeontx_fc_info { + enum rte_eth_fc_mode mode; /**< Link flow control mode */ + enum rte_eth_fc_mode def_mode; + uint16_t high_water; + uint16_t low_water; + uint16_t def_highmark; + uint16_t def_lowmark; + uint32_t rx_fifosz; +}; + /* Octeontx ethdev nic */ struct octeontx_nic { struct rte_eth_dev *dev; @@ -122,6 +132,7 @@ struct octeontx_nic { uint16_t tx_offload_flags; struct octeontx_vlan_info vlan_info; int print_flag; + struct octeontx_fc_info fc; } __rte_cache_aligned; struct octeontx_txq { @@ -154,4 +165,12 @@ int octeontx_dev_vlan_filter_set(struct rte_eth_dev *dev, int octeontx_dev_set_link_up(struct rte_eth_dev *eth_dev); int octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev); +/* Flow control */ +int octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev); +int octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev); +int octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); +int octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); + #endif /* __OCTEONTX_ETHDEV_H__ */ diff --git a/drivers/net/octeontx/octeontx_ethdev_ops.c b/drivers/net/octeontx/octeontx_ethdev_ops.c index b5f0bfe8a..ff627a68e 100644 --- a/drivers/net/octeontx/octeontx_ethdev_ops.c +++ b/drivers/net/octeontx/octeontx_ethdev_ops.c @@ -213,3 +213,131 @@ octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev) return octeontx_bgx_port_set_link_state(nic->port_id, false); } + +int +octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + octeontx_mbox_bgx_port_fc_cfg_t conf; + int rc; + + memset(&conf, 0, sizeof(octeontx_mbox_bgx_port_fc_cfg_t)); + + rc = octeontx_bgx_port_flow_ctrl_cfg(nic->port_id, &conf); + if (rc) + return rc; + + if (conf.rx_pause && conf.tx_pause) + fc_conf->mode = RTE_FC_FULL; + else if (conf.rx_pause) + fc_conf->mode = RTE_FC_RX_PAUSE; + else if (conf.tx_pause) + fc_conf->mode = RTE_FC_TX_PAUSE; + else + fc_conf->mode = RTE_FC_NONE; + + /* low_water & high_water values are in Bytes */ + fc_conf->low_water = conf.low_water; + fc_conf->high_water = conf.high_water; + + return rc; +} + +int +octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + struct octeontx_fc_info *fc = &nic->fc; + octeontx_mbox_bgx_port_fc_cfg_t conf; + uint8_t tx_pause, rx_pause; + uint16_t max_high_water; + int rc; + + if (fc_conf->pause_time || fc_conf->mac_ctrl_frame_fwd || + fc_conf->autoneg) { + octeontx_log_err("Below flowctrl parameters are not supported " + "pause_time, mac_ctrl_frame_fwd and autoneg"); + return -EINVAL; + } + + if (fc_conf->high_water == fc->high_water && + fc_conf->low_water == fc->low_water && + fc_conf->mode == fc->mode) + return 0; + + max_high_water = fc->rx_fifosz - OCTEONTX_BGX_RSVD_RX_FIFOBYTES; + + if (fc_conf->high_water > max_high_water || + fc_conf->high_water < fc_conf->low_water) { + octeontx_log_err("Invalid high/low water values " + "High_water(in Bytes) must <= 0x%x ", + max_high_water); + return -EINVAL; + } + + if (fc_conf->high_water % BIT(4) || fc_conf->low_water % BIT(4)) { + octeontx_log_err("High/low water value must be multiple of 16"); + return -EINVAL; + } + + rx_pause = (fc_conf->mode == RTE_FC_FULL) || + (fc_conf->mode == RTE_FC_RX_PAUSE); + tx_pause = (fc_conf->mode == RTE_FC_FULL) || + (fc_conf->mode == RTE_FC_TX_PAUSE); + + conf.high_water = fc_conf->high_water; + conf.low_water = fc_conf->low_water; + conf.fc_cfg = BGX_PORT_FC_CFG_SET; + conf.rx_pause = rx_pause; + conf.tx_pause = tx_pause; + + rc = octeontx_bgx_port_flow_ctrl_cfg(nic->port_id, &conf); + if (rc) + return rc; + + fc->high_water = fc_conf->high_water; + fc->low_water = fc_conf->low_water; + fc->mode = fc_conf->mode; + + return rc; +} + +int +octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + struct octeontx_fc_info *fc = &nic->fc; + struct rte_eth_fc_conf fc_conf; + int rc; + + rc = octeontx_dev_flow_ctrl_get(dev, &fc_conf); + if (rc) { + octeontx_log_err("Failed to get flow control info"); + return rc; + } + + fc->def_highmark = fc_conf.high_water; + fc->def_lowmark = fc_conf.low_water; + fc->def_mode = fc_conf.mode; + + return rc; +} + +int +octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + struct octeontx_fc_info *fc = &nic->fc; + struct rte_eth_fc_conf fc_conf; + + memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf)); + + /* Restore flow control parameters with default values */ + fc_conf.high_water = fc->def_highmark; + fc_conf.low_water = fc->def_lowmark; + fc_conf.mode = fc->def_mode; + + return octeontx_dev_flow_ctrl_set(dev, &fc_conf); +} -- 2.18.0