From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7042A00C3; Sat, 16 May 2020 11:28:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3218D1D9CE; Sat, 16 May 2020 11:27:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7094E1D9C9 for ; Sat, 16 May 2020 11:27:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 04G9QBsv020926; Sat, 16 May 2020 02:27:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=MrGy7q4Wt6NBeaxdn1oW9DV2TS4l4iuctGli8IJP8ro=; b=PcE17DDBMwlaAcVSgizzlvUO427BWFs59F6kkp/52ac8rlM08sB/VMKktVPOsmMLeYmV 6wvC4Rfksp4AzctJi/JZ+RfOQLGca5yvUqTkP5CESoAes/Pklpo+MZxkd0H2pqjFiag4 XSAK54Xd/1Re0C5L1n3mJzSRfWkCkw5vNmsW244CIJfk/PgawzeUiWVmQkzPKUC9xvPe ZXD6vR35BHAR/kH/vXpHSMfCWuKw0Md47rqa282i+eXZklYDRHgB09uL3yq+JiKxzPeh fSwqwihIvCd82u6C3pFF9xT4NWNx1CMAMVN5oqWzqvLmpo0eBqwKOsSR2w+KKK005keB 3g== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3100xkbrfw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 16 May 2020 02:27:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 16 May 2020 02:27:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 16 May 2020 02:27:38 -0700 Received: from ajoseph83.caveonetworks.com (ajoseph83.caveonetworks.com [10.29.45.60]) by maili.marvell.com (Postfix) with ESMTP id 30BF23F7040; Sat, 16 May 2020 02:27:35 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal CC: Ankur Dwivedi , Thomas Monjalon , Jerin Jacob , Narayana Prasad , Tejasree Kondoj , , Anoob Joseph Date: Sat, 16 May 2020 14:56:57 +0530 Message-ID: <1589621218-25339-6-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589621218-25339-1-git-send-email-anoobj@marvell.com> References: <1589621218-25339-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.676 definitions=2020-05-16_05:2020-05-15, 2020-05-16 signatures=0 Subject: [dpdk-dev] [PATCH 5/6] crypto/octeontx: enable non-byte aligned data feature X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi The OCTEON TX crypto PMD supports non-byte aligned data as input for SNOW and ZUC algos. Adding the same to the feature list. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph --- doc/guides/cryptodevs/features/octeontx.ini | 1 + drivers/crypto/octeontx/otx_cryptodev_ops.c | 1 + 2 files changed, 2 insertions(+) diff --git a/doc/guides/cryptodevs/features/octeontx.ini b/doc/guides/cryptodevs/features/octeontx.ini index 4ce4ff1..09affb2 100644 --- a/doc/guides/cryptodevs/features/octeontx.ini +++ b/doc/guides/cryptodevs/features/octeontx.ini @@ -13,6 +13,7 @@ OOP SGL In LB Out = Y OOP SGL In SGL Out = Y RSA PRIV OP KEY QT = Y Symmetric sessionless = Y +Non-Byte aligned data = Y ; ; Supported crypto algorithms of 'octeontx' crypto driver. diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c index 3fbf5d5..7097499 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c @@ -968,6 +968,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev) RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | + RTE_CRYPTODEV_FF_NON_BYTE_ALIGNED_DATA | RTE_CRYPTODEV_FF_SYM_SESSIONLESS; break; default: -- 2.7.4