From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7BBB6A053D; Fri, 17 Jul 2020 12:29:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 99A461C0B6; Fri, 17 Jul 2020 12:28:36 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 5A21E1BFC4 for ; Fri, 17 Jul 2020 12:28:26 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from orika@mellanox.com) with SMTP; 17 Jul 2020 13:28:25 +0300 Received: from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx [10.210.16.126]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06HARt8Y001211; Fri, 17 Jul 2020 13:28:24 +0300 From: Ori Kam To: jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com, viacheslavo@mellanox.com Cc: guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com, shahafs@mellanox.com, hemant.agrawal@nxp.com, opher@mellanox.com, alexr@mellanox.com, dovrat@marvell.com, pkapoor@marvell.com, nipun.gupta@nxp.com, bruce.richardson@intel.com, yang.a.hong@intel.com, harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn, zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com, wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com, davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com, oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org, fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net, orika@mellanox.com, rasland@mellanox.com Date: Fri, 17 Jul 2020 10:27:46 +0000 Message-Id: <1594981672-156840-9-git-send-email-orika@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1594981672-156840-1-git-send-email-orika@mellanox.com> References: <1593941027-86651-1-git-send-email-orika@mellanox.com> <1594981672-156840-1-git-send-email-orika@mellanox.com> Subject: [dpdk-dev] [PATCH v3 08/13] regex/mlx5: add completion queue creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds the creation of CQ Signed-off-by: Ori Kam --- drivers/regex/mlx5/Makefile | 1 + drivers/regex/mlx5/meson.build | 1 + drivers/regex/mlx5/mlx5_regex.c | 1 + drivers/regex/mlx5/mlx5_regex.h | 4 +- drivers/regex/mlx5/mlx5_regex_control.c | 195 ++++++++++++++++++++++++++++++++ drivers/regex/mlx5/mlx5_rxp.c | 1 + 6 files changed, 201 insertions(+), 2 deletions(-) create mode 100644 drivers/regex/mlx5/mlx5_regex_control.c diff --git a/drivers/regex/mlx5/Makefile b/drivers/regex/mlx5/Makefile index 0de38e5..806db99 100644 --- a/drivers/regex/mlx5/Makefile +++ b/drivers/regex/mlx5/Makefile @@ -10,6 +10,7 @@ LIB = librte_pmd_mlx5_regex.a SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex.c SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_rxp.c SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex_devx.c +SRCS-$(CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD) += mlx5_regex_control.c # Basic CFLAGS. CFLAGS += -O3 diff --git a/drivers/regex/mlx5/meson.build b/drivers/regex/mlx5/meson.build index dd75fe7..6f01df7 100644 --- a/drivers/regex/mlx5/meson.build +++ b/drivers/regex/mlx5/meson.build @@ -13,6 +13,7 @@ sources = files( 'mlx5_regex.c', 'mlx5_rxp.c', 'mlx5_regex_devx.c', + 'mlx5_regex_control.c', ) cflags_options = [ '-std=c11', diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index d6629bc..f8a9562 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -25,6 +25,7 @@ .dev_info_get = mlx5_regex_info_get, .dev_configure = mlx5_regex_configure, .dev_db_import = mlx5_regex_rules_db_import, + .dev_qp_setup = mlx5_regex_qp_setup, }; static struct ibv_device * diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 3334198..e1e0b4d 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -19,7 +19,7 @@ struct mlx5_regex_sq { struct mlx5_devx_obj *obj; /* The SQ DevX object. */ int64_t dbr_offset; /* Door bell record offset. */ uint32_t dbr_umem; /* Door bell record umem id. */ - volatile struct mlx5_cqe *wqe; /* The SQ ring buffer. */ + uint8_t *wqe; /* The SQ ring buffer. */ struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */ }; @@ -62,10 +62,10 @@ struct mlx5_regex_priv { struct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES + MLX5_RXP_EM_COUNT]; uint32_t nb_engines; /* Number of RegEx engines. */ - struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ uint32_t eqn; /* EQ number. */ struct mlx5dv_devx_uar *uar; /* UAR object. */ struct ibv_pd *pd; + struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ }; /* mlx5_rxp.c */ diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c new file mode 100644 index 0000000..577965f --- /dev/null +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 Mellanox Technologies, Ltd + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "mlx5_regex.h" +#include "mlx5_regex_utils.h" +#include "mlx5_rxp_csrs.h" +#include "mlx5_rxp.h" + +#define MLX5_REGEX_NUM_WQE_PER_PAGE (4096/64) + +/** + * Returns the number of qp obj to be created. + * + * @param nb_desc + * The number of descriptors for the queue. + * + * @return + * The number of obj to be created. + */ +static uint16_t +regex_ctrl_get_nb_obj(uint16_t nb_desc) +{ + return ((nb_desc / MLX5_REGEX_NUM_WQE_PER_PAGE) + + !!(nb_desc % MLX5_REGEX_NUM_WQE_PER_PAGE)); +} + +/** + * destroy CQ. + * + * @param priv + * Pointer to the priv object. + * @param cp + * Pointer to the CQ to be destroyed. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +regex_ctrl_destroy_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq) +{ + if (cq->cqe_umem) { + mlx5_glue->devx_umem_dereg(cq->cqe_umem); + cq->cqe_umem = NULL; + } + if (cq->cqe) { + rte_free((void *)(uintptr_t)cq->cqe); + cq->cqe = NULL; + } + if (cq->dbr_offset) { + mlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset); + cq->dbr_offset = -1; + } + if (cq->obj) { + mlx5_devx_cmd_destroy(cq->obj); + cq->obj = NULL; + } + return 0; +} + +/** + * create the CQ object. + * + * @param priv + * Pointer to the priv object. + * @param cp + * Pointer to the CQ to be created. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq) +{ + struct mlx5_devx_cq_attr attr = { + .q_umem_valid = 1, + .db_umem_valid = 1, + .eqn = priv->eqn, + }; + struct mlx5_devx_dbr_page *dbr_page = NULL; + void *buf = NULL; + size_t pgsize = sysconf(_SC_PAGESIZE); + uint32_t cq_size = 1 << cq->log_nb_desc; + uint32_t i; + + cq->dbr_offset = mlx5_get_dbr(priv->ctx, &priv->dbrpgs, &dbr_page); + if (cq->dbr_offset < 0) { + DRV_LOG(ERR, "Can't allocate cq door bell record."); + rte_errno = ENOMEM; + goto error; + } + cq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem); + buf = rte_calloc(NULL, 1, sizeof(struct mlx5_cqe) * cq_size, 4096); + if (!buf) { + DRV_LOG(ERR, "Can't allocate cqe buffer."); + rte_errno = ENOMEM; + goto error; + } + cq->cqe = buf; + for (i = 0; i < cq_size; i++) + cq->cqe[i].op_own = 0xff; + cq->cqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf, + sizeof(struct mlx5_cqe) * + cq_size, 7); + if (!cq->cqe_umem) { + DRV_LOG(ERR, "Can't register cqe mem."); + rte_errno = ENOMEM; + goto error; + } + attr.db_umem_offset = cq->dbr_offset; + attr.db_umem_id = cq->dbr_umem; + attr.q_umem_id = mlx5_os_get_umem_id(cq->cqe_umem); + attr.log_cq_size = cq->log_nb_desc; + attr.uar_page_id = priv->uar->page_id; + attr.log_page_size = rte_log2_u32(pgsize); + cq->obj = mlx5_devx_cmd_create_cq(priv->ctx, &attr); + if (!cq->obj) { + DRV_LOG(ERR, "Can't create cq object."); + rte_errno = ENOMEM; + goto error; + } + return 0; +error: + if (cq->cqe_umem) + mlx5_glue->devx_umem_dereg(cq->cqe_umem); + if (buf) + rte_free(buf); + if (cq->dbr_offset) + mlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset); + return -rte_errno; +} + +/** + * Setup the qp. + * + * @param dev + * Pointer to RegEx dev structure. + * @param qp_ind + * The queue index to setup. + * @param cfg + * The queue requested configuration. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, + const struct rte_regexdev_qp_conf *cfg) +{ + struct mlx5_regex_priv *priv = dev->data->dev_private; + struct mlx5_regex_qp *qp; + int ret; + + qp = &priv->qps[qp_ind]; + qp->flags = cfg->qp_conf_flags; + qp->cq.log_nb_desc = rte_log2_u32(cfg->nb_desc); + qp->nb_desc = 1 << qp->cq.log_nb_desc; + if (qp->flags & RTE_REGEX_QUEUE_PAIR_CFG_OOS_F) + qp->nb_obj = regex_ctrl_get_nb_obj(qp->nb_desc); + else + qp->nb_obj = 1; + qp->sqs = rte_malloc(NULL, + qp->nb_obj * sizeof(struct mlx5_regex_sq), 64); + if (!qp->sqs) { + DRV_LOG(ERR, "Can't allocate sq array memory."); + rte_errno = ENOMEM; + return -rte_errno; + } + ret = regex_ctrl_create_cq(priv, &qp->cq); + if (ret) { + DRV_LOG(ERR, "Can't create cq."); + goto error; + } + return 0; + +error: + regex_ctrl_destroy_cq(priv, &qp->cq); + return -rte_errno; + +} diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c index 5dfba26..b8fab79 100644 --- a/drivers/regex/mlx5/mlx5_rxp.c +++ b/drivers/regex/mlx5/mlx5_rxp.c @@ -118,6 +118,7 @@ info->max_queue_pairs = 1; info->regexdev_capa = RTE_REGEXDEV_SUPP_PCRE_GREEDY_F; info->rule_flags = 0; + info->max_queue_pairs = 10; return 0; } -- 1.8.3.1