From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3B282A0526; Tue, 21 Jul 2020 13:32:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F278B1C037; Tue, 21 Jul 2020 13:32:07 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 110751C037 for ; Tue, 21 Jul 2020 13:32:04 +0200 (CEST) IronPort-SDR: 2+q+U/ttkKOnRXS3wIuPuqbTyirIxWwWkfU/hJTCtxNGygcTSgy7ra+Ng+mdzufLG6FwI36Ymg id99aD9PcgWw== X-IronPort-AV: E=McAfee;i="6000,8403,9688"; a="214767024" X-IronPort-AV: E=Sophos;i="5.75,378,1589266800"; d="scan'208";a="214767024" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2020 04:32:04 -0700 IronPort-SDR: U4iBUmVAjs0/Wd1ndTAWdFALx9HubWI2urkl2MVlwn9fnYRDQPo6Ai3eeM8rf40FyVWYV41cn2 Adp4lnwLs28g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,378,1589266800"; d="scan'208";a="462041842" Received: from silpixa00383879.ir.intel.com ([10.237.222.142]) by orsmga005.jf.intel.com with ESMTP; 21 Jul 2020 04:32:02 -0700 From: Radu Nicolau To: dev@dpdk.org Cc: beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, jerinjacobk@gmail.com, david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com, ruifeng.wang@arm.com, Radu Nicolau Date: Tue, 21 Jul 2020 12:31:50 +0100 Message-Id: <1595331111-12151-4-git-send-email-radu.nicolau@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595331111-12151-1-git-send-email-radu.nicolau@intel.com> References: <1591870283-7776-1-git-send-email-radu.nicolau@intel.com> <1595331111-12151-1-git-send-email-radu.nicolau@intel.com> Subject: [dpdk-dev] [PATCH v10 3/4] common/qat: use WC store to update queue tail registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Performance improvement: use a write combining store instead of a regular mmio write to update queue tail registers. Signed-off-by: Radu Nicolau Acked-by: Fiona Trahe --- drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h index 1eef551..504ffb7 100644 --- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h +++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h @@ -9,6 +9,8 @@ /* CSR write macro */ #define ADF_CSR_WR(csrAddr, csrOffset, val) \ rte_write32(val, (((uint8_t *)csrAddr) + csrOffset)) +#define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \ + rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset)) /* CSR read macro */ #define ADF_CSR_RD(csrAddr, csrOffset) \ @@ -110,10 +112,10 @@ do { \ ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \ } while (0) #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ - ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ + ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ ADF_RING_CSR_RING_HEAD + (ring << 2), value) #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ - ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ + ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ ADF_RING_CSR_RING_TAIL + (ring << 2), value) #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ do { \ -- 2.7.4