From: Yuval Avnery <yuvalav@mellanox.com>
To: Matan Azrad <matan@mellanox.com>,
Shahaf Shuler <shahafs@mellanox.com>,
Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Cc: thomas@monjalon.net, dev@dpdk.org, yuvalav@mellanox.com,
orika@mellanox.com
Subject: [dpdk-dev] [PATCH v1] common/mlx5: fix set regex register layout
Date: Tue, 28 Jul 2020 17:50:44 +0000 [thread overview]
Message-ID: <1595958644-66526-1-git-send-email-yuvalav@mellanox.com> (raw)
Reserved field should be 0x60 instead of 0x40.
Will fail FW check otherwise.
Fixes: be4f4a8b8e3b ("regex/mlx5: add engine status check")
Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
---
drivers/common/mlx5/mlx5_prm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 8fab962..c78b462 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2789,7 +2789,7 @@ struct mlx5_ifc_set_regexp_register_in_bits {
u8 engine_id[0x8];
u8 register_address[0x20];
u8 register_data[0x20];
- u8 reserved[0x40];
+ u8 reserved[0x60];
};
struct mlx5_ifc_set_regexp_register_out_bits {
--
1.8.3.1
next reply other threads:[~2020-07-28 17:50 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-28 17:50 Yuval Avnery [this message]
2020-07-29 15:01 ` Raslan Darawsheh
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