From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD902A04AC; Mon, 24 Aug 2020 10:42:05 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3BC9B1C0AE; Mon, 24 Aug 2020 10:42:01 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id B0CD31C07D for ; Mon, 24 Aug 2020 10:41:59 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2714911B3; Mon, 24 Aug 2020 01:41:59 -0700 (PDT) Received: from phil-VirtualBox.shanghai.arm.com (phil-VirtualBox.shanghai.arm.com [10.169.37.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C405C3F68F; Mon, 24 Aug 2020 01:41:55 -0700 (PDT) From: Phil Yang To: dev@dpdk.org Cc: jerinj@marvell.com, drc@linux.vnet.ibm.com, ajit.khaparde@broadcom.com, konstantin.ananyev@intel.com, honnappa.nagarahalli@arm.com, joyce.kong@arm.com, nd@arm.com, Jan Viktorin , Ruifeng Wang , Bruce Richardson Date: Mon, 24 Aug 2020 16:40:41 +0800 Message-Id: <1598258441-15696-2-git-send-email-phil.yang@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598258441-15696-1-git-send-email-phil.yang@arm.com> References: <1598258441-15696-1-git-send-email-phil.yang@arm.com> Subject: [dpdk-dev] [PATCH 2/2] eal: remove RTE CIO barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove the deprecated rte_cio_[rw]mb APIs. Signed-off-by: Phil Yang Reviewed-by: Ruifeng Wang --- lib/librte_eal/arm/include/rte_atomic_32.h | 4 --- lib/librte_eal/arm/include/rte_atomic_64.h | 4 --- lib/librte_eal/include/generic/rte_atomic.h | 39 ----------------------------- lib/librte_eal/ppc/include/rte_atomic.h | 4 --- lib/librte_eal/x86/include/rte_atomic.h | 4 --- 5 files changed, 55 deletions(-) diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h b/lib/librte_eal/arm/include/rte_atomic_32.h index 368f10c..9d0568d 100644 --- a/lib/librte_eal/arm/include/rte_atomic_32.h +++ b/lib/librte_eal/arm/include/rte_atomic_32.h @@ -33,10 +33,6 @@ extern "C" { #define rte_io_rmb() rte_rmb() -#define rte_cio_wmb() rte_wmb() - -#define rte_cio_rmb() rte_rmb() - static __rte_always_inline void rte_atomic_thread_fence(int memory_order) { diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h index 5cae52d..c518559 100644 --- a/lib/librte_eal/arm/include/rte_atomic_64.h +++ b/lib/librte_eal/arm/include/rte_atomic_64.h @@ -37,10 +37,6 @@ extern "C" { #define rte_io_rmb() rte_rmb() -#define rte_cio_wmb() rte_wmb() - -#define rte_cio_rmb() rte_rmb() - static __rte_always_inline void rte_atomic_thread_fence(int memory_order) { diff --git a/lib/librte_eal/include/generic/rte_atomic.h b/lib/librte_eal/include/generic/rte_atomic.h index 95270f1..d1255b2 100644 --- a/lib/librte_eal/include/generic/rte_atomic.h +++ b/lib/librte_eal/include/generic/rte_atomic.h @@ -107,45 +107,6 @@ static inline void rte_io_wmb(void); static inline void rte_io_rmb(void); ///@} -/** @name Coherent I/O Memory Barrier - * - * Coherent I/O memory barrier is a lightweight version of I/O memory - * barriers which are system-wide data synchronization barriers. This - * is for only coherent memory domain between lcore and I/O device but - * it is same as the I/O memory barriers in most of architectures. - * However, some architecture provides even lighter barriers which are - * somewhere in between I/O memory barriers and SMP memory barriers. - * For example, in case of ARMv8, DMB(data memory barrier) instruction - * can have different shareability domains - inner-shareable and - * outer-shareable. And inner-shareable DMB fits for SMP memory - * barriers and outer-shareable DMB for coherent I/O memory barriers, - * which acts on coherent memory. - * - * In most cases, I/O memory barriers are safer but if operations are - * on coherent memory instead of incoherent MMIO region of a device, - * then coherent I/O memory barriers can be used and this could bring - * performance gain depending on architectures. - */ -///@{ -/** - * Write memory barrier for coherent memory between lcore and I/O device - * - * Guarantees that the STORE operations on coherent memory that - * precede the rte_cio_wmb() call are visible to I/O device before the - * STORE operations that follow it. - */ -static inline void rte_cio_wmb(void); - -/** - * Read memory barrier for coherent memory between lcore and I/O device - * - * Guarantees that the LOAD operations on coherent memory updated by - * I/O device that precede the rte_cio_rmb() call are visible to CPU - * before the LOAD operations that follow it. - */ -static inline void rte_cio_rmb(void); -///@} - #endif /* __DOXYGEN__ */ /** diff --git a/lib/librte_eal/ppc/include/rte_atomic.h b/lib/librte_eal/ppc/include/rte_atomic.h index 527fcaf..a919899 100644 --- a/lib/librte_eal/ppc/include/rte_atomic.h +++ b/lib/librte_eal/ppc/include/rte_atomic.h @@ -36,10 +36,6 @@ extern "C" { #define rte_io_rmb() rte_rmb() -#define rte_cio_wmb() rte_wmb() - -#define rte_cio_rmb() rte_rmb() - static __rte_always_inline void rte_atomic_thread_fence(int memory_order) { diff --git a/lib/librte_eal/x86/include/rte_atomic.h b/lib/librte_eal/x86/include/rte_atomic.h index 62ea393..b7d6b06 100644 --- a/lib/librte_eal/x86/include/rte_atomic.h +++ b/lib/librte_eal/x86/include/rte_atomic.h @@ -79,10 +79,6 @@ rte_smp_mb(void) #define rte_io_rmb() rte_compiler_barrier() -#define rte_cio_wmb() rte_compiler_barrier() - -#define rte_cio_rmb() rte_compiler_barrier() - /** * Synchronization fence between threads based on the specified memory order. * -- 2.7.4