From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 31556A052A; Wed, 27 Jan 2021 03:16:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 63931140DA3; Wed, 27 Jan 2021 03:16:41 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 57509140D9D; Wed, 27 Jan 2021 03:16:38 +0100 (CET) IronPort-SDR: IEWUzj5PWihmDRqYa5Zo/mPaZzA0SnCVEfoEihooxMtzlS3J7HAZ0FJl8HNOPD0oyNsr4dPhbo Yhqbl4whud/g== X-IronPort-AV: E=McAfee;i="6000,8403,9876"; a="244082017" X-IronPort-AV: E=Sophos;i="5.79,378,1602572400"; d="scan'208";a="244082017" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2021 18:16:34 -0800 IronPort-SDR: tbocDJK1Cb3z8JRMz2d6r+06AgdnaF8LCYEnkf5YsUz+rFrLlrzH/wMUyBO8nPdo5WSgAiWgph p1UY483njBpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,378,1602572400"; d="scan'208";a="410365500" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by FMSMGA003.fm.intel.com with ESMTP; 26 Jan 2021 18:16:34 -0800 Received: from shsmsx604.ccr.corp.intel.com (10.109.6.214) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 26 Jan 2021 18:16:32 -0800 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by SHSMSX604.ccr.corp.intel.com (10.109.6.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 27 Jan 2021 10:16:30 +0800 Received: from shsmsx603.ccr.corp.intel.com ([10.109.6.143]) by SHSMSX603.ccr.corp.intel.com ([10.109.6.143]) with mapi id 15.01.1713.004; Wed, 27 Jan 2021 10:16:30 +0800 From: "Yu, DapengX" To: "Xing, Beilei" , "Guo, Jia" CC: "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [PATCH] net/i40e: fix register setting for hash enable Thread-Index: AQHW88jz4bnLAwBaskykWVwkny1gM6o6Li+AgACJgeA= Date: Wed, 27 Jan 2021 02:16:30 +0000 Message-ID: <159b0b86360f454dbb6e2f94bb42eeba@intel.com> References: <20210126095211.628354-1-dapengx.yu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: fix register setting for hash enable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Beilei, The pctype translation is introduced by i40e RSS refactor commit: ef4c16fd9= 148 by mistake, its behavior is inconsistent with the implementation before= the refactor.=20 This inconsistency can be gotten from the comparison of the running of the = code. I have also confirmed with the author of commit: ef4c16fd9148 that the addi= ng of the translation is a mistake.=20 So actually even if without x722 datasheet, we can know the translation is = unnecessary. I cannot find x722 datasheet from Intel website. It will be great if you ca= n share one. Thanks! -----Original Message----- From: Xing, Beilei=20 Sent: Wednesday, January 27, 2021 9:44 AM To: Yu, DapengX ; Guo, Jia Cc: dev@dpdk.org; Yu, DapengX ; stable@dpdk.org Subject: RE: [PATCH] net/i40e: fix register setting for hash enable > -----Original Message----- > From: dapengx.yu@intel.com > Sent: Tuesday, January 26, 2021 5:52 PM > To: Xing, Beilei ; Guo, Jia > Cc: dev@dpdk.org; Yu, DapengX ; stable@dpdk.org > Subject: [PATCH] net/i40e: fix register setting for hash enable >=20 > From: Dapeng Yu >=20 > The original code causes wrong value to be set into PFQF_HENA register=20 > because unnecessary calling to get translated pctype value for X722=20 > NIC. The result is RSS cannot work. >=20 > So remove the unnecessary translation. >=20 > Fixes: ef4c16fd9148 ("net/i40e: refactor RSS flow") > Cc: stable@dpdk.org >=20 > Signed-off-by: Dapeng Yu > --- > drivers/net/i40e/i40e_hash.c | 4 ---- > 1 file changed, 4 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_hash.c=20 > b/drivers/net/i40e/i40e_hash.c index > 9271797a7..b1cb24f43 100644 > --- a/drivers/net/i40e/i40e_hash.c > +++ b/drivers/net/i40e/i40e_hash.c > @@ -678,10 +678,6 @@ i40e_hash_enable_pctype(struct i40e_hw *hw, { =20 > uint32_t reg, reg_val, mask; >=20 > -/* For X722, get translated pctype in fd pctype register */ -if=20 > (hw->mac.type =3D=3D I40E_MAC_X722) -pctype =3D i40e_read_rx_ctl(hw,=20 > I40E_GLQF_FD_PCTYPES(pctype)); > - Did you check the latest X722 datasheet to confirm the behavior? > if (pctype < 32) { > mask =3D BIT(pctype); > reg =3D I40E_PFQF_HENA(0); > -- > 2.27.0