From: Michael Baum <michaelba@nvidia.com>
To: dev@dpdk.org
Cc: Matan Azrad <matan@nvidia.com>,
Raslan Darawsheh <rasland@nvidia.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
stable@dpdk.org
Subject: [dpdk-dev] [PATCH v1 2/2] net/mlx5: fix using hairpin without dest DevX TIR support
Date: Sun, 13 Sep 2020 19:05:22 +0000 [thread overview]
Message-ID: <1600023922-14738-2-git-send-email-michaelba@nvidia.com> (raw)
In-Reply-To: <1600023922-14738-1-git-send-email-michaelba@nvidia.com>
The PMD supports hairpin only if DevX is supported and DV flow is enable.
When destination DevX TIR is not supported, the PMD tries to create TIR
action, and fails.
Avoid supporting hairpin when destination DevX TIR is not supported.
Fixes: b6b3bf86bd1a ("net/mlx5: get hairpin capabilities")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/mlx5_ethdev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index cefb450..a7924b1 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -569,12 +569,12 @@ struct mlx5_priv *
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
-mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
- struct rte_eth_hairpin_cap *cap)
+mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)
{
struct mlx5_priv *priv = dev->data->dev_private;
+ struct mlx5_dev_config *config = &priv->config;
- if (priv->sh->devx == 0) {
+ if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) {
rte_errno = ENOTSUP;
return -rte_errno;
}
--
1.8.3.1
next prev parent reply other threads:[~2020-09-13 19:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-13 19:05 [dpdk-dev] [PATCH v1 1/2] net/mlx5: fix Rx objects creator selection Michael Baum
2020-09-13 19:05 ` Michael Baum [this message]
2020-09-15 13:37 ` Raslan Darawsheh
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