From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B980FA04E1; Tue, 22 Sep 2020 10:54:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C9C311DB4A; Tue, 22 Sep 2020 10:50:59 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id F3D511D710 for ; Tue, 22 Sep 2020 10:50:19 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.143]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 6EF7120051 for ; Tue, 22 Sep 2020 08:50:19 +0000 (UTC) Received: from us4-mdac16-12.at1.mdlocal (unknown [10.110.49.194]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 6E82B8009B for ; Tue, 22 Sep 2020 08:50:19 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.7]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id E45C74006E for ; Tue, 22 Sep 2020 08:50:18 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 96C164C005D for ; Tue, 22 Sep 2020 08:50:18 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Sep 2020 09:50:10 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Sep 2020 09:50:10 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08M8oAw4004692 for ; Tue, 22 Sep 2020 09:50:10 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 678721613AB for ; Tue, 22 Sep 2020 09:50:10 +0100 (BST) From: Andrew Rybchenko To: Date: Tue, 22 Sep 2020 09:49:20 +0100 Message-ID: <1600764594-14752-27-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600764594-14752-1-git-send-email-arybchenko@solarflare.com> References: <1600764594-14752-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25674.003 X-TM-AS-Result: No-3.072000-8.000000-10 X-TMASE-MatchedRID: TzL0DiA+Z4tKsq30PQsu2y2416nc3bQleouvej40T4gOW0St5DT4VHnU bFaXoymefGzuoVn0Vs6PQi9XuOWoOHI/MxNRI7UkRaPXfvn+kerxuhkRWK22GEyQ8hzF3nP27vf jHqfMw2InecByCGCjWThb430fp9B3Tj/OlUrKzKxlpwNsTvdlKWI1A430gHPy75lKyW2tHKQ8fE 8eLil3XqzZ04T+Xb+BoXB0muO4iv6lqWyS1oruBDCMW7zNwFaI2u3GDhv7CuxfUCHPns/+PuSww /zZZINV8DSmZP4m2sIRNFuSPBxpFl8citbqy06TltBnppfPmLpQdXu/xf76ufpw6p0dDLzheWwY le3v1YyH9eJA08ufnpsajzKCYJAHB47Cx1EiwG2lI6wRbGpulQokziiS8fleeoHKBqqMb3GjxYy RBa/qJft6/2HgfIgDVymkLM+r7VTGVuWouVipcrewSLvhmlqfbcGmwV7uE7aXytKy0JjjZavHpf +TtKg7xu3TQC4IZ+gEcaJNiAlUGT2G5mrzWmYEehOFMgDoKDiXowehMoihp0+9nKAUfbd9OiMMf iztpo/4XWZPvl2TZLAodBnVXNL5k0Q6cxt5OvU= X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.072000-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25674.003 X-MDID: 1600764619-Ehs1bUF2JLaG Subject: [dpdk-dev] [PATCH 26/60] common/sfc_efx/base: move RxQ init/fini wrappers to generic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" RxQ init/fini MCDI is similar on Riverhead and these functions should be reused to implement RxQ creation and destruction on Riverhead. Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- drivers/common/sfc_efx/base/ef10_rx.c | 184 ------------------------ drivers/common/sfc_efx/base/efx_impl.h | 28 ++++ drivers/common/sfc_efx/base/efx_mcdi.c | 187 +++++++++++++++++++++++++ 3 files changed, 215 insertions(+), 184 deletions(-) diff --git a/drivers/common/sfc_efx/base/ef10_rx.c b/drivers/common/sfc_efx/base/ef10_rx.c index bfa55337c2..f27058963f 100644 --- a/drivers/common/sfc_efx/base/ef10_rx.c +++ b/drivers/common/sfc_efx/base/ef10_rx.c @@ -10,190 +10,6 @@ #if EFX_OPTS_EF10() - -static __checkReturn efx_rc_t -efx_mcdi_init_rxq( - __in efx_nic_t *enp, - __in uint32_t ndescs, - __in efx_evq_t *eep, - __in uint32_t label, - __in uint32_t instance, - __in efsys_mem_t *esmp, - __in boolean_t disable_scatter, - __in boolean_t want_inner_classes, - __in uint32_t buf_size, - __in uint32_t ps_bufsize, - __in uint32_t es_bufs_per_desc, - __in uint32_t es_max_dma_len, - __in uint32_t es_buf_stride, - __in uint32_t hol_block_timeout) -{ - efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - efx_mcdi_req_t req; - EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V4_IN_LEN, - MC_CMD_INIT_RXQ_V4_OUT_LEN); - int npages = efx_rxq_nbufs(enp, ndescs); - int i; - efx_qword_t *dma_addr; - uint64_t addr; - efx_rc_t rc; - uint32_t dma_mode; - boolean_t want_outer_classes; - boolean_t no_cont_ev; - - EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs); - - if ((esmp == NULL) || - (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) { - rc = EINVAL; - goto fail1; - } - - no_cont_ev = (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV); - if ((no_cont_ev == B_TRUE) && (disable_scatter == B_FALSE)) { - /* TODO: Support scatter in NO_CONT_EV mode */ - rc = EINVAL; - goto fail2; - } - - if (ps_bufsize > 0) - dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM; - else if (es_bufs_per_desc > 0) - dma_mode = MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER; - else - dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET; - - if (encp->enc_tunnel_encapsulations_supported != 0 && - !want_inner_classes) { - /* - * WANT_OUTER_CLASSES can only be specified on hardware which - * supports tunnel encapsulation offloads, even though it is - * effectively the behaviour the hardware gives. - * - * Also, on hardware which does support such offloads, older - * firmware rejects the flag if the offloads are not supported - * by the current firmware variant, which means this may fail if - * the capabilities are not updated when the firmware variant - * changes. This is not an issue on newer firmware, as it was - * changed in bug 69842 (v6.4.2.1007) to permit this flag to be - * specified on all firmware variants. - */ - want_outer_classes = B_TRUE; - } else { - want_outer_classes = B_FALSE; - } - - req.emr_cmd = MC_CMD_INIT_RXQ; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_INIT_RXQ_V4_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_INIT_RXQ_V4_OUT_LEN; - - MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs); - MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, eep->ee_index); - MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label); - MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance); - MCDI_IN_POPULATE_DWORD_10(req, INIT_RXQ_EXT_IN_FLAGS, - INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0, - INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0, - INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0, - INIT_RXQ_EXT_IN_CRC_MODE, 0, - INIT_RXQ_EXT_IN_FLAG_PREFIX, 1, - INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter, - INIT_RXQ_EXT_IN_DMA_MODE, - dma_mode, - INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize, - INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes, - INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV, no_cont_ev); - MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0); - MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, enp->en_vport_id); - - if (es_bufs_per_desc > 0) { - MCDI_IN_SET_DWORD(req, - INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET, - es_bufs_per_desc); - MCDI_IN_SET_DWORD(req, - INIT_RXQ_V3_IN_ES_MAX_DMA_LEN, es_max_dma_len); - MCDI_IN_SET_DWORD(req, - INIT_RXQ_V3_IN_ES_PACKET_STRIDE, es_buf_stride); - MCDI_IN_SET_DWORD(req, - INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT, - hol_block_timeout); - } - - if (encp->enc_init_rxq_with_buffer_size) - MCDI_IN_SET_DWORD(req, INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES, - buf_size); - - dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR); - addr = EFSYS_MEM_ADDR(esmp); - - for (i = 0; i < npages; i++) { - EFX_POPULATE_QWORD_2(*dma_addr, - EFX_DWORD_1, (uint32_t)(addr >> 32), - EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); - - dma_addr++; - addr += EFX_BUF_SIZE; - } - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail3; - } - - return (0); - -fail3: - EFSYS_PROBE(fail3); -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, efx_rc_t, rc); - - return (rc); -} - -static __checkReturn efx_rc_t -efx_mcdi_fini_rxq( - __in efx_nic_t *enp, - __in uint32_t instance) -{ - efx_mcdi_req_t req; - EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_RXQ_IN_LEN, - MC_CMD_FINI_RXQ_OUT_LEN); - efx_rc_t rc; - - req.emr_cmd = MC_CMD_FINI_RXQ; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN; - - MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance); - - efx_mcdi_execute_quiet(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; - goto fail1; - } - - return (0); - -fail1: - /* - * EALREADY is not an error, but indicates that the MC has rebooted and - * that the RXQ has already been destroyed. - */ - if (rc != EALREADY) - EFSYS_PROBE1(fail1, efx_rc_t, rc); - - return (rc); -} - #if EFSYS_OPT_RX_SCALE static __checkReturn efx_rc_t efx_mcdi_rss_context_alloc( diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h index f6b0850a65..48f853cf91 100644 --- a/drivers/common/sfc_efx/base/efx_impl.h +++ b/drivers/common/sfc_efx/base/efx_impl.h @@ -1430,6 +1430,34 @@ efx_mcdi_fini_evq( #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ +#if EFX_OPTS_EF10() + +LIBEFX_INTERNAL +extern __checkReturn efx_rc_t +efx_mcdi_init_rxq( + __in efx_nic_t *enp, + __in uint32_t ndescs, + __in efx_evq_t *eep, + __in uint32_t label, + __in uint32_t instance, + __in efsys_mem_t *esmp, + __in boolean_t disable_scatter, + __in boolean_t want_inner_classes, + __in uint32_t buf_size, + __in uint32_t ps_bufsize, + __in uint32_t es_bufs_per_desc, + __in uint32_t es_max_dma_len, + __in uint32_t es_buf_stride, + __in uint32_t hol_block_timeout); + +LIBEFX_INTERNAL +extern __checkReturn efx_rc_t +efx_mcdi_fini_rxq( + __in efx_nic_t *enp, + __in uint32_t instance); + +#endif /* EFX_OPTS_EF10() */ + #endif /* EFSYS_OPT_MCDI */ #if EFSYS_OPT_MAC_STATS diff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c index 841dacc1c8..8bf7c86c3a 100644 --- a/drivers/common/sfc_efx/base/efx_mcdi.c +++ b/drivers/common/sfc_efx/base/efx_mcdi.c @@ -2682,4 +2682,191 @@ efx_mcdi_fini_evq( #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ +#if EFX_OPTS_EF10() + + __checkReturn efx_rc_t +efx_mcdi_init_rxq( + __in efx_nic_t *enp, + __in uint32_t ndescs, + __in efx_evq_t *eep, + __in uint32_t label, + __in uint32_t instance, + __in efsys_mem_t *esmp, + __in boolean_t disable_scatter, + __in boolean_t want_inner_classes, + __in uint32_t buf_size, + __in uint32_t ps_bufsize, + __in uint32_t es_bufs_per_desc, + __in uint32_t es_max_dma_len, + __in uint32_t es_buf_stride, + __in uint32_t hol_block_timeout) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_mcdi_req_t req; + EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V4_IN_LEN, + MC_CMD_INIT_RXQ_V4_OUT_LEN); + int npages = efx_rxq_nbufs(enp, ndescs); + int i; + efx_qword_t *dma_addr; + uint64_t addr; + efx_rc_t rc; + uint32_t dma_mode; + boolean_t want_outer_classes; + boolean_t no_cont_ev; + + EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs); + + if ((esmp == NULL) || + (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) { + rc = EINVAL; + goto fail1; + } + + no_cont_ev = (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV); + if ((no_cont_ev == B_TRUE) && (disable_scatter == B_FALSE)) { + /* TODO: Support scatter in NO_CONT_EV mode */ + rc = EINVAL; + goto fail2; + } + + if (ps_bufsize > 0) + dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM; + else if (es_bufs_per_desc > 0) + dma_mode = MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER; + else + dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET; + + if (encp->enc_tunnel_encapsulations_supported != 0 && + !want_inner_classes) { + /* + * WANT_OUTER_CLASSES can only be specified on hardware which + * supports tunnel encapsulation offloads, even though it is + * effectively the behaviour the hardware gives. + * + * Also, on hardware which does support such offloads, older + * firmware rejects the flag if the offloads are not supported + * by the current firmware variant, which means this may fail if + * the capabilities are not updated when the firmware variant + * changes. This is not an issue on newer firmware, as it was + * changed in bug 69842 (v6.4.2.1007) to permit this flag to be + * specified on all firmware variants. + */ + want_outer_classes = B_TRUE; + } else { + want_outer_classes = B_FALSE; + } + + req.emr_cmd = MC_CMD_INIT_RXQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_INIT_RXQ_V4_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_INIT_RXQ_V4_OUT_LEN; + + MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs); + MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, eep->ee_index); + MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label); + MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance); + MCDI_IN_POPULATE_DWORD_10(req, INIT_RXQ_EXT_IN_FLAGS, + INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0, + INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0, + INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0, + INIT_RXQ_EXT_IN_CRC_MODE, 0, + INIT_RXQ_EXT_IN_FLAG_PREFIX, 1, + INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter, + INIT_RXQ_EXT_IN_DMA_MODE, + dma_mode, + INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize, + INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes, + INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV, no_cont_ev); + MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0); + MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, enp->en_vport_id); + + if (es_bufs_per_desc > 0) { + MCDI_IN_SET_DWORD(req, + INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET, + es_bufs_per_desc); + MCDI_IN_SET_DWORD(req, + INIT_RXQ_V3_IN_ES_MAX_DMA_LEN, es_max_dma_len); + MCDI_IN_SET_DWORD(req, + INIT_RXQ_V3_IN_ES_PACKET_STRIDE, es_buf_stride); + MCDI_IN_SET_DWORD(req, + INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT, + hol_block_timeout); + } + + if (encp->enc_init_rxq_with_buffer_size) + MCDI_IN_SET_DWORD(req, INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES, + buf_size); + + dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR); + addr = EFSYS_MEM_ADDR(esmp); + + for (i = 0; i < npages; i++) { + EFX_POPULATE_QWORD_2(*dma_addr, + EFX_DWORD_1, (uint32_t)(addr >> 32), + EFX_DWORD_0, (uint32_t)(addr & 0xffffffff)); + + dma_addr++; + addr += EFX_BUF_SIZE; + } + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail3; + } + + return (0); + +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + + __checkReturn efx_rc_t +efx_mcdi_fini_rxq( + __in efx_nic_t *enp, + __in uint32_t instance) +{ + efx_mcdi_req_t req; + EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_RXQ_IN_LEN, + MC_CMD_FINI_RXQ_OUT_LEN); + efx_rc_t rc; + + req.emr_cmd = MC_CMD_FINI_RXQ; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN; + + MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance); + + efx_mcdi_execute_quiet(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + /* + * EALREADY is not an error, but indicates that the MC has rebooted and + * that the RXQ has already been destroyed. + */ + if (rc != EALREADY) + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + +#endif /* EFX_OPTS_EF10() */ + #endif /* EFSYS_OPT_MCDI */ -- 2.17.1