From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42933A04E1; Tue, 22 Sep 2020 10:54:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 922181DB45; Tue, 22 Sep 2020 10:50:58 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 380CF1D724 for ; Tue, 22 Sep 2020 10:50:20 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.150]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id D0EBB2006D for ; Tue, 22 Sep 2020 08:50:19 +0000 (UTC) Received: from us4-mdac16-60.at1.mdlocal (unknown [10.110.50.153]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id D00B3800A3 for ; Tue, 22 Sep 2020 08:50:19 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.7]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 7749D100052 for ; Tue, 22 Sep 2020 08:50:19 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 40CAB4C005C for ; Tue, 22 Sep 2020 08:50:19 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Sep 2020 09:50:11 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Sep 2020 09:50:11 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08M8oAPw004736 for ; Tue, 22 Sep 2020 09:50:10 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id D69C41613AB for ; Tue, 22 Sep 2020 09:50:10 +0100 (BST) From: Andrew Rybchenko To: Date: Tue, 22 Sep 2020 09:49:28 +0100 Message-ID: <1600764594-14752-35-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600764594-14752-1-git-send-email-arybchenko@solarflare.com> References: <1600764594-14752-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25674.003 X-TM-AS-Result: No-4.697000-8.000000-10 X-TMASE-MatchedRID: 0pxx+/g/BD+39BLh6Bkc7jIjK23O9D33iK5qg1cmsr98Tu6cvkQQvKEG Khm9baaN2XHJ0L4jOIQs/31GzKkTsQihmwiXCMoGPwKTD1v8YV5MkOX0UoduuUXdikJnBDss6+3 41imwtEUvXg8b+phJFmOoqp5MGQKzGm91h6WPksYovbifIQL7GlBijjE0XjY+MTkWY9HYyZE4Cu qwY18cov0g2ay/3atluewO5rBHdH4fE8yM4pjsDwtuKBGekqUpnH7sbImOEBSwUgGq48Acxi36L DbK+BiWkEw6gK6BLxzC5v+NGA9CzKfk5FJQ7AN0RumpyZBuN/jEZGlPJHZyVTv3SaSWNZQKnhj7 AbDzKkovOSq+nxEQtagePGmIEwXO/4UC4n7D3uWJl6tigvYfL0uFvzEYSdV+ X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.697000-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25674.003 X-MDID: 1600764619-du6YuIwNRCt6 Subject: [dpdk-dev] [PATCH 34/60] common/sfc_efx/base: fix Tx descriptor DMA sync on Riverhead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Rx/Tx queue DMA sync should not assume descriptor size to be the same for all NIC familties since it Tx descritor size is 16 on Riverhead. Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- drivers/common/sfc_efx/base/ef10_rx.c | 2 +- drivers/common/sfc_efx/base/ef10_tx.c | 4 ++-- drivers/common/sfc_efx/base/efx_impl.h | 9 +++++---- drivers/common/sfc_efx/base/efx_rx.c | 2 +- drivers/common/sfc_efx/base/efx_tx.c | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/common/sfc_efx/base/ef10_rx.c b/drivers/common/sfc_efx/base/ef10_rx.c index 61e0dab5b9..2f0d2d2f5b 100644 --- a/drivers/common/sfc_efx/base/ef10_rx.c +++ b/drivers/common/sfc_efx/base/ef10_rx.c @@ -693,7 +693,7 @@ ef10_rx_qpush( /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1, - wptr, pushed & erp->er_mask); + EF10_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask); EFSYS_PIO_WRITE_BARRIER(); EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG, erp->er_index, &dword, B_FALSE); diff --git a/drivers/common/sfc_efx/base/ef10_tx.c b/drivers/common/sfc_efx/base/ef10_tx.c index 61c7e49fe8..7cc9324b4b 100644 --- a/drivers/common/sfc_efx/base/ef10_tx.c +++ b/drivers/common/sfc_efx/base/ef10_tx.c @@ -375,7 +375,7 @@ ef10_tx_qpush( /* Ensure ordering of memory (descriptors) and PIO (doorbell) */ EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, - wptr, id); + EF10_TXQ_DESC_SIZE, wptr, id); EFSYS_PIO_WRITE_BARRIER(); EFX_BAR_VI_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index, &oword); @@ -391,7 +391,7 @@ ef10_tx_qpush( /* Ensure ordering of memory (descriptors) and PIO (doorbell) */ EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, - wptr, id); + EF10_TXQ_DESC_SIZE, wptr, id); EFSYS_PIO_WRITE_BARRIER(); EFX_BAR_VI_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index, &dword, B_FALSE); diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h index d7e11c6323..52f974073f 100644 --- a/drivers/common/sfc_efx/base/efx_impl.h +++ b/drivers/common/sfc_efx/base/efx_impl.h @@ -1292,15 +1292,16 @@ struct efx_txq_s { _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) -#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ +#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \ + _wptr, _owptr) \ do { \ unsigned int _new = (_wptr); \ unsigned int _old = (_owptr); \ \ if ((_new) >= (_old)) \ EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ - (_old) * sizeof (efx_desc_t), \ - ((_new) - (_old)) * sizeof (efx_desc_t)); \ + (_old) * (_desc_size), \ + ((_new) - (_old)) * (_desc_size)); \ else \ /* \ * It is cheaper to sync entire map than sync \ @@ -1309,7 +1310,7 @@ struct efx_txq_s { */ \ EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 0, \ - (_entries) * sizeof (efx_desc_t)); \ + (_entries) * (_desc_size)); \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) diff --git a/drivers/common/sfc_efx/base/efx_rx.c b/drivers/common/sfc_efx/base/efx_rx.c index 5f17bf3afe..14eda45f4a 100644 --- a/drivers/common/sfc_efx/base/efx_rx.c +++ b/drivers/common/sfc_efx/base/efx_rx.c @@ -1581,7 +1581,7 @@ siena_rx_qpush( /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1, - wptr, pushed & erp->er_mask); + SIENA_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask); EFSYS_PIO_WRITE_BARRIER(); EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0, erp->er_index, &dword, B_FALSE); diff --git a/drivers/common/sfc_efx/base/efx_tx.c b/drivers/common/sfc_efx/base/efx_tx.c index d7f31fd46d..d9568bf4a6 100644 --- a/drivers/common/sfc_efx/base/efx_tx.c +++ b/drivers/common/sfc_efx/base/efx_tx.c @@ -866,7 +866,7 @@ siena_tx_qpush( /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */ EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, - wptr, pushed & etp->et_mask); + SIENA_TXQ_DESC_SIZE, wptr, pushed & etp->et_mask); EFSYS_PIO_WRITE_BARRIER(); EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0, etp->et_index, &dword, B_FALSE); -- 2.17.1