From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C2B4A04B1; Thu, 24 Sep 2020 14:16:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4B6891DE90; Thu, 24 Sep 2020 14:13:36 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id A19E71DE0D for ; Thu, 24 Sep 2020 14:12:57 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.64]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 2E12960083 for ; Thu, 24 Sep 2020 12:12:57 +0000 (UTC) Received: from us4-mdac16-6.ut7.mdlocal (unknown [10.7.65.74]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 2D0CC2009B for ; Thu, 24 Sep 2020 12:12:57 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.174]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id A55D4220056 for ; Thu, 24 Sep 2020 12:12:56 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 5B7871C0064 for ; Thu, 24 Sep 2020 12:12:56 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 24 Sep 2020 13:12:46 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:46 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08OCCkX4025946 for ; Thu, 24 Sep 2020 13:12:46 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id C37A71613A9 for ; Thu, 24 Sep 2020 13:12:46 +0100 (BST) From: Andrew Rybchenko To: Date: Thu, 24 Sep 2020 13:11:56 +0100 Message-ID: <1600949555-28043-22-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600949555-28043-1-git-send-email-arybchenko@solarflare.com> References: <1600764594-14752-1-git-send-email-arybchenko@solarflare.com> <1600949555-28043-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25674.003 X-TM-AS-Result: No-1.215400-8.000000-10 X-TMASE-MatchedRID: 9hBAAcW/nSDbiFIWuP4ar6iUivh0j2PvhVDnkfzD7uYHZBaLwEXlKN4z BXBaIg4K9iW+JthsPhN5OcPpd8LBNcd68wmyGhe2h2VzUlo4HVNSDnPEI8clbQJjWCvDD6tZunq 41dm00Wf5tdT54pJb82n0e2dnzzMtTflYhYHA+jRFo9d++f6R6p3ZbPRfc5otmyiLZetSf8mfop 0ytGwvXiq2rl3dzGQ1libS7WAAZr9CkoQ3TrrrzSCR7g3PL9UZkBvv3Iz0NmGEcZ4oftQlRduM/ vtpO0w7PcSgQgcHldpqeqD8gC3wHR/ljgYu5qFf/IM1A2WUbTIjoqQAvYDmRwy1ivD0G5PCpKZI 9GApJky6jC8l0hZCbkMMprcbiest X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.215400-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25674.003 X-MDID: 1600949577-aSPE023f-uA0 Subject: [dpdk-dev] [PATCH v3 21/60] common/sfc_efx/base: prepare to merge EvQ init functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" v1 and v2 defines are the same except output length. Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- drivers/common/sfc_efx/base/efx_mcdi.c | 52 +++++++++++++------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c index 5b733bb88c..50d723ecb4 100644 --- a/drivers/common/sfc_efx/base/efx_mcdi.c +++ b/drivers/common/sfc_efx/base/efx_mcdi.c @@ -2458,8 +2458,8 @@ efx_mcdi_init_evq( { efx_mcdi_req_t req; EFX_MCDI_DECLARE_BUF(payload, - MC_CMD_INIT_EVQ_IN_LEN(EF10_EVQ_MAXNBUFS), - MC_CMD_INIT_EVQ_OUT_LEN); + MC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS), + MC_CMD_INIT_EVQ_V2_OUT_LEN); efx_qword_t *dma_addr; uint64_t addr; int npages; @@ -2476,13 +2476,13 @@ efx_mcdi_init_evq( req.emr_cmd = MC_CMD_INIT_EVQ; req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages); + req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages); req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN; + req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN; - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs); - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance); - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq); interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) == EFX_EVQ_FLAGS_NOTIFY_INTERRUPT); @@ -2509,37 +2509,37 @@ efx_mcdi_init_evq( rc = EINVAL; goto fail2; } - MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS, - INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting, - INIT_EVQ_IN_FLAG_RPTR_DOS, 0, - INIT_EVQ_IN_FLAG_INT_ARMD, 0, - INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through, - INIT_EVQ_IN_FLAG_RX_MERGE, 1, - INIT_EVQ_IN_FLAG_TX_MERGE, 1); + MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_V2_IN_FLAGS, + INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting, + INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0, + INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0, + INIT_EVQ_V2_IN_FLAG_CUT_THRU, ev_cut_through, + INIT_EVQ_V2_IN_FLAG_RX_MERGE, 1, + INIT_EVQ_V2_IN_FLAG_TX_MERGE, 1); /* If the value is zero then disable the timer */ if (us == 0) { - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE, - MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0); - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE, + MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0); } else { unsigned int ticks; if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0) goto fail3; - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE, - MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF); - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks); - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE, + MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks); } - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE, - MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); - MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE, + MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS); + MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0); - dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR); + dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR); addr = EFSYS_MEM_ADDR(esmp); for (i = 0; i < npages; i++) { -- 2.17.1