From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D62BAA04BC; Tue, 29 Sep 2020 17:14:05 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4C80E1D6CA; Tue, 29 Sep 2020 17:13:29 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 55DAC1D6A5 for ; Tue, 29 Sep 2020 17:13:21 +0200 (CEST) IronPort-SDR: Pyz3/MMqMzYqVFpEAeg5V87mNGFEtiLkNASouKG5Xes/ZnB1A6tFHmB6bFTitScNMIvZJdSEOR nI0UzJT7O6pw== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="180367537" X-IronPort-AV: E=Sophos;i="5.77,319,1596524400"; d="scan'208";a="180367537" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2020 08:13:17 -0700 IronPort-SDR: 6NrG35hThuMF3szjW2achx+qsQiWFbmr9Xn/qczVKzCyH4fd2w+E003ybNM2KyBK9Sy0R5OGxM SgitX8cHX4mA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,319,1596524400"; d="scan'208";a="345300546" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 29 Sep 2020 08:13:15 -0700 Received: from sivswdev08.ir.intel.com (sivswdev08.ir.intel.com [10.237.217.47]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 08TFDEg8003281; Tue, 29 Sep 2020 16:13:14 +0100 Received: from sivswdev08.ir.intel.com (localhost [127.0.0.1]) by sivswdev08.ir.intel.com with ESMTP id 08TFDEXm023044; Tue, 29 Sep 2020 16:13:14 +0100 Received: (from moloings@localhost) by sivswdev08.ir.intel.com with LOCAL id 08TFDECd023040; Tue, 29 Sep 2020 16:13:14 +0100 From: Mairtin o Loingsigh To: jasvinder.singh@intel.com, bruce.richardson@intel.com, pablo.de.lara.guarch@intel.com Cc: dev@dpdk.org, brendan.ryan@intel.com, david.coyle@intel.com, Mairtin o Loingsigh Date: Tue, 29 Sep 2020 16:12:45 +0100 Message-Id: <1601392366-22625-2-git-send-email-mairtin.oloingsigh@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1599739271-16605-1-git-send-email-mairtin.oloingsigh@intel.com> References: <1599739271-16605-1-git-send-email-mairtin.oloingsigh@intel.com> Subject: [dpdk-dev] [PATCH v2 1/2] net: add run-time architecture specific CRC selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds support for run-time selection of the optimal architecture-specific CRC path, based on the supported instruction set(s) of the CPU. The compiler option checks have been moved from the C files to the meson script. The rte_cpu_get_flag_enabled function is called automatically by the library at process initialization time to determine which instructions the CPU supports, with the most optimal supported CRC path ultimately selected. Signed-off-by: Mairtin o Loingsigh Signed-off-by: David Coyle --- doc/guides/rel_notes/release_20_11.rst | 4 ++ lib/librte_net/meson.build | 34 +++++++++++- lib/librte_net/net_crc.h | 34 ++++++++++++ lib/librte_net/{net_crc_neon.h => net_crc_neon.c} | 27 +++------ lib/librte_net/{net_crc_sse.h => net_crc_sse.c} | 34 ++++-------- lib/librte_net/rte_net_crc.c | 67 ++++++++++++++--------- 6 files changed, 132 insertions(+), 68 deletions(-) create mode 100644 lib/librte_net/net_crc.h rename lib/librte_net/{net_crc_neon.h => net_crc_neon.c} (95%) rename lib/librte_net/{net_crc_sse.h => net_crc_sse.c} (94%) diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index 4eb3224a7..6bd222dca 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -55,6 +55,10 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated CRC modules of rte_net library.** + + * Added run-time selection of the optimal architecture-specific CRC path. + * **Updated Cisco enic driver.** * Added support for VF representors with single-queue Tx/Rx and flow API diff --git a/lib/librte_net/meson.build b/lib/librte_net/meson.build index 24ed8253b..b6880bd85 100644 --- a/lib/librte_net/meson.build +++ b/lib/librte_net/meson.build @@ -1,5 +1,5 @@ # SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2017 Intel Corporation +# Copyright(c) 2017-2020 Intel Corporation headers = files('rte_ip.h', 'rte_tcp.h', @@ -20,3 +20,35 @@ headers = files('rte_ip.h', sources = files('rte_arp.c', 'rte_ether.c', 'rte_net.c', 'rte_net_crc.c') deps += ['mbuf'] + +if dpdk_conf.has('RTE_ARCH_X86_64') + net_crc_sse42_cpu_support = \ + cc.get_define('__PCLMUL__', args: machine_args) != '' + net_crc_sse42_cc_support = \ + cc.has_argument('-mpclmul') and cc.has_argument('-maes') + + build_static_net_crc_sse42_lib = 0 + + if net_crc_sse42_cpu_support == true + sources += files('net_crc_sse.c') + cflags += ['-DCC_X86_64_SSE42_PCLMULQDQ_SUPPORT'] + elif net_crc_sse42_cc_support == true + build_static_net_crc_sse42_lib = 1 + net_crc_sse42_lib_cflags = ['-mpclmul', '-maes'] + cflags += ['-DCC_X86_64_SSE42_PCLMULQDQ_SUPPORT'] + endif + + if build_static_net_crc_sse42_lib == 1 + net_crc_sse42_lib = static_library( + 'net_crc_sse42_lib', + 'net_crc_sse.c', + dependencies: static_rte_eal, + c_args: [cflags, + net_crc_sse42_lib_cflags]) + objs += net_crc_sse42_lib.extract_objects('net_crc_sse.c') + endif +elif dpdk_conf.has('RTE_ARCH_ARM64') and \ + cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != '' + sources += files('net_crc_neon.c') + cflags += ['-DCC_ARM64_NEON_PMULL_SUPPORT'] +endif diff --git a/lib/librte_net/net_crc.h b/lib/librte_net/net_crc.h new file mode 100644 index 000000000..a1578a56c --- /dev/null +++ b/lib/librte_net/net_crc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2020 Intel Corporation + */ + +#ifndef _NET_CRC_H_ +#define _NET_CRC_H_ + +/* + * Different implementations of CRC + */ + +/* SSE4.2 */ + +void +rte_net_crc_sse42_init(void); + +uint32_t +rte_crc16_ccitt_sse42_handler(const uint8_t *data, uint32_t data_len); + +uint32_t +rte_crc32_eth_sse42_handler(const uint8_t *data, uint32_t data_len); + +/* NEON */ + +void +rte_net_crc_neon_init(void); + +uint32_t +rte_crc16_ccitt_neon_handler(const uint8_t *data, uint32_t data_len); + +uint32_t +rte_crc32_eth_neon_handler(const uint8_t *data, uint32_t data_len); + +#endif /* _NET_CRC_H_ */ diff --git a/lib/librte_net/net_crc_neon.h b/lib/librte_net/net_crc_neon.c similarity index 95% rename from lib/librte_net/net_crc_neon.h rename to lib/librte_net/net_crc_neon.c index 63fa1d4a1..b79684ec2 100644 --- a/lib/librte_net/net_crc_neon.h +++ b/lib/librte_net/net_crc_neon.c @@ -1,18 +1,17 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2017 Cavium, Inc + * Copyright(c) 2020 Intel Corporation */ -#ifndef _NET_CRC_NEON_H_ -#define _NET_CRC_NEON_H_ +#include +#include #include #include #include #include -#ifdef __cplusplus -extern "C" { -#endif +#include "net_crc.h" /** PMULL CRC computation context structure */ struct crc_pmull_ctx { @@ -218,7 +217,7 @@ crc32_eth_calc_pmull( return n; } -static inline void +void rte_net_crc_neon_init(void) { /* Initialize CRC16 data */ @@ -242,9 +241,8 @@ rte_net_crc_neon_init(void) crc32_eth_pmull.rk7_rk8 = vld1q_u64(eth_k7_k8); } -static inline uint32_t -rte_crc16_ccitt_neon_handler(const uint8_t *data, - uint32_t data_len) +uint32_t +rte_crc16_ccitt_neon_handler(const uint8_t *data, uint32_t data_len) { return (uint16_t)~crc32_eth_calc_pmull(data, data_len, @@ -252,18 +250,11 @@ rte_crc16_ccitt_neon_handler(const uint8_t *data, &crc16_ccitt_pmull); } -static inline uint32_t -rte_crc32_eth_neon_handler(const uint8_t *data, - uint32_t data_len) +uint32_t +rte_crc32_eth_neon_handler(const uint8_t *data, uint32_t data_len) { return ~crc32_eth_calc_pmull(data, data_len, 0xffffffffUL, &crc32_eth_pmull); } - -#ifdef __cplusplus -} -#endif - -#endif /* _NET_CRC_NEON_H_ */ diff --git a/lib/librte_net/net_crc_sse.h b/lib/librte_net/net_crc_sse.c similarity index 94% rename from lib/librte_net/net_crc_sse.h rename to lib/librte_net/net_crc_sse.c index 1c7b7a548..053b54b39 100644 --- a/lib/librte_net/net_crc_sse.h +++ b/lib/librte_net/net_crc_sse.c @@ -1,18 +1,16 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2017 Intel Corporation + * Copyright(c) 2017-2020 Intel Corporation */ -#ifndef _RTE_NET_CRC_SSE_H_ -#define _RTE_NET_CRC_SSE_H_ +#include +#include #include +#include -#include -#include +#include "net_crc.h" -#ifdef __cplusplus -extern "C" { -#endif +#include /** PCLMULQDQ CRC computation context structure */ struct crc_pclmulqdq_ctx { @@ -259,8 +257,7 @@ crc32_eth_calc_pclmulqdq( return n; } - -static inline void +void rte_net_crc_sse42_init(void) { uint64_t k1, k2, k5, k6; @@ -303,12 +300,10 @@ rte_net_crc_sse42_init(void) * use other data types such as float, double, etc. */ _mm_empty(); - } -static inline uint32_t -rte_crc16_ccitt_sse42_handler(const uint8_t *data, - uint32_t data_len) +uint32_t +rte_crc16_ccitt_sse42_handler(const uint8_t *data, uint32_t data_len) { /** return 16-bit CRC value */ return (uint16_t)~crc32_eth_calc_pclmulqdq(data, @@ -317,18 +312,11 @@ rte_crc16_ccitt_sse42_handler(const uint8_t *data, &crc16_ccitt_pclmulqdq); } -static inline uint32_t -rte_crc32_eth_sse42_handler(const uint8_t *data, - uint32_t data_len) +uint32_t +rte_crc32_eth_sse42_handler(const uint8_t *data, uint32_t data_len) { return ~crc32_eth_calc_pclmulqdq(data, data_len, 0xffffffffUL, &crc32_eth_pclmulqdq); } - -#ifdef __cplusplus -} -#endif - -#endif /* _RTE_NET_CRC_SSE_H_ */ diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c index 4f5b9e828..83dccbfba 100644 --- a/lib/librte_net/rte_net_crc.c +++ b/lib/librte_net/rte_net_crc.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2017 Intel Corporation + * Copyright(c) 2017-2020 Intel Corporation */ #include @@ -10,17 +10,7 @@ #include #include -#if defined(RTE_ARCH_X86_64) && defined(__PCLMUL__) -#define X86_64_SSE42_PCLMULQDQ 1 -#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRYPTO) -#define ARM64_NEON_PMULL 1 -#endif - -#ifdef X86_64_SSE42_PCLMULQDQ -#include -#elif defined ARM64_NEON_PMULL -#include -#endif +#include "net_crc.h" /** CRC polynomials */ #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL @@ -47,13 +37,13 @@ static rte_net_crc_handler handlers_scalar[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler, [RTE_NET_CRC32_ETH] = rte_crc32_eth_handler, }; - -#ifdef X86_64_SSE42_PCLMULQDQ +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT static rte_net_crc_handler handlers_sse42[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler, [RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler, }; -#elif defined ARM64_NEON_PMULL +#endif +#ifdef CC_ARM64_NEON_PMULL_SUPPORT static rte_net_crc_handler handlers_neon[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler, [RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler, @@ -142,22 +132,44 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len) crc32_eth_lut); } +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT +static uint8_t +sse42_pclmulqdq_cpu_supported(void) +{ + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ); +} +#endif + +#ifdef CC_ARM64_NEON_PMULL_SUPPORT +static uint8_t +neon_pmull_cpu_supported(void) +{ + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL); +} +#endif + void rte_net_crc_set_alg(enum rte_net_crc_alg alg) { switch (alg) { -#ifdef X86_64_SSE42_PCLMULQDQ +#ifdef RTE_ARCH_X86_64 case RTE_NET_CRC_SSE42: - handlers = handlers_sse42; - break; -#elif defined ARM64_NEON_PMULL - /* fall-through */ +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT + if (sse42_pclmulqdq_cpu_supported()) { + handlers = handlers_sse42; + break; + } +#endif +#endif /* RTE_ARCH_X86_64 */ +#ifdef RTE_ARCH_ARM64 case RTE_NET_CRC_NEON: - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { +#ifdef CC_ARM64_NEON_PMULL_SUPPORT + if (neon_pmull_cpu_supported()) { handlers = handlers_neon; break; } #endif +#endif /* RTE_ARCH_ARM64 */ /* fall-through */ case RTE_NET_CRC_SCALAR: /* fall-through */ @@ -188,11 +200,14 @@ RTE_INIT(rte_net_crc_init) rte_net_crc_scalar_init(); -#ifdef X86_64_SSE42_PCLMULQDQ - alg = RTE_NET_CRC_SSE42; - rte_net_crc_sse42_init(); -#elif defined ARM64_NEON_PMULL - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT + if (sse42_pclmulqdq_cpu_supported()) { + alg = RTE_NET_CRC_SSE42; + rte_net_crc_sse42_init(); + } +#endif +#ifdef CC_ARM64_NEON_PMULL_SUPPORT + if (neon_pmull_cpu_supported()) { alg = RTE_NET_CRC_NEON; rte_net_crc_neon_init(); } -- 2.12.3