From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D65D8A04DB; Thu, 15 Oct 2020 08:39:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 324551DCB2; Thu, 15 Oct 2020 08:38:37 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 2E70A1DC84 for ; Thu, 15 Oct 2020 08:38:30 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from matan@nvidia.com) with SMTP; 15 Oct 2020 09:38:23 +0300 Received: from nvidia.com (pegasus25.mtr.labs.mlnx [10.210.16.10]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09F6cNVu014993; Thu, 15 Oct 2020 09:38:23 +0300 From: Matan Azrad To: dev@dpdk.org Cc: Viacheslav Ovsiienko , stable@dpdk.org Date: Thu, 15 Oct 2020 06:38:12 +0000 Message-Id: <1602743893-345348-3-git-send-email-matan@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1602743893-345348-1-git-send-email-matan@nvidia.com> References: <1602743893-345348-1-git-send-email-matan@nvidia.com> Subject: [dpdk-dev] [PATCH 3/4] net/mlx5: fix event queue number query X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When a Rx\Tx queue is created by DevX, its CQ configuration should include the EQ number of the interrupts. The EQ is managed by the kernel and there is a glue API in order to query the EQ number from the kernel. The EQ query API gets a vector number specifies the kernel vector of the interrupt handling. The vector number was wrongly detected according to the configuration CPU instead of using the device attributes of the supported vectors. The CPU was wrongly detected by the rte_lcore_to_cpu_id API without any check, and in case of non-EAL thread context the value was 0xFFFFFFFF which caused a failure in the EQ number query API. Use vector 0 for each EQ number query which must be supported by the kernel. Fixes: 08d1838f645a ("net/mlx5: implement CQ for Rx using DevX API") Fixes: d133f4cdb706 ("net/mlx5: create clock queue for packet pacing") Cc: stable@dpdk.org Signed-off-by: Matan Azrad Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 44822ad..f1e3579 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -947,10 +947,8 @@ struct mlx5_dev_ctx_shared * goto error; } if (sh->devx) { - uint32_t lcore = (uint32_t)rte_lcore_to_cpu_id(-1); - /* Query the EQN for this core. */ - err = mlx5_glue->devx_query_eqn(sh->ctx, lcore, &sh->eqn); + err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn); if (err) { rte_errno = errno; DRV_LOG(ERR, "Failed to query event queue number %d.", -- 1.8.3.1