From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03EEFA04DD; Tue, 20 Oct 2020 11:26:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C55A4CFB1; Tue, 20 Oct 2020 11:14:48 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 71727C806 for ; Tue, 20 Oct 2020 11:14:10 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.60]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id E083560050 for ; Tue, 20 Oct 2020 09:14:08 +0000 (UTC) Received: from us4-mdac16-63.ut7.mdlocal (unknown [10.7.66.62]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id DFB292009A for ; Tue, 20 Oct 2020 09:14:08 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.66.41]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 640CC1C004F for ; Tue, 20 Oct 2020 09:14:08 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 188484C0071 for ; Tue, 20 Oct 2020 09:14:08 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Oct 2020 10:14:00 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Oct 2020 10:14:00 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09K9DxUB028392; Tue, 20 Oct 2020 10:13:59 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id CFABE1613AB; Tue, 20 Oct 2020 10:13:59 +0100 (BST) From: Andrew Rybchenko To: CC: Ivan Malov Date: Tue, 20 Oct 2020 10:12:59 +0100 Message-ID: <1603185222-14831-20-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1603185222-14831-1-git-send-email-arybchenko@solarflare.com> References: <1603183709-23420-1-git-send-email-arybchenko@solarflare.com> <1603185222-14831-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25736.003 X-TM-AS-Result: No-1.355500-8.000000-10 X-TMASE-MatchedRID: pm5esiOnALWqfSQfLa/SN6iUivh0j2Pv6VTG9cZxEjIGmHr1eMxt2UAc 6DyoS2rIEcE+LOiKuIt27cZtoykdFo9y28rShcKqRpZ38TWrY5yoSgRE9rhqi08iLpubparmku+ GdcB8c5O+9mDuGGWszi83jj4qEbKvxz6opuAAUJIPe5gzF3TVt9ST/TZ3TTpFbdiWoEZixCujxY yRBa/qJcFwgTvxipFajoczmuoPCq2TinQiJ4LphjPnD9L3bIRZjt+BvEYBmOOpyJ8n9mqyBGJBT U6nDmRgIZinM5iiFn4uPYpo5rd4OnMsjZzimveuNMpshF9F2MGF15h6/oibNbKsWJ44GuEGPNxa u39/BitFwHZmk+dWMmhnUCrcDtVn X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.355500-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25736.003 X-MDID: 1603185248-u0JpIh2VdKTc X-PPE-DISP: 1603185248;u0JpIh2VdKTc Subject: [dpdk-dev] [PATCH v2 19/62] net/sfc: support flow item ETH in MAE backend X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ivan Malov Add support for this flow item to MAE-specific RTE flow implementation. Signed-off-by: Ivan Malov Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- doc/guides/nics/sfc_efx.rst | 2 + drivers/net/sfc/sfc_mae.c | 106 ++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/doc/guides/nics/sfc_efx.rst b/doc/guides/nics/sfc_efx.rst index b12e93180e..65d52d5551 100644 --- a/doc/guides/nics/sfc_efx.rst +++ b/doc/guides/nics/sfc_efx.rst @@ -192,6 +192,8 @@ Supported pattern items (***transfer*** rules): - PHY_PORT (cannot repeat; conflicts with other traffic source items) +- ETH + Validating flow rules depends on the firmware variant. The :ref:`flow_isolated_mode` is supported. diff --git a/drivers/net/sfc/sfc_mae.c b/drivers/net/sfc/sfc_mae.c index 87d2e15d29..95f8cffc27 100644 --- a/drivers/net/sfc/sfc_mae.c +++ b/drivers/net/sfc/sfc_mae.c @@ -221,6 +221,105 @@ sfc_mae_rule_parse_item_phy_port(const struct rte_flow_item *item, return 0; } +struct sfc_mae_field_locator { + efx_mae_field_id_t field_id; + size_t size; + /* Field offset in the corresponding rte_flow_item_ struct */ + size_t ofst; +}; + +static void +sfc_mae_item_build_supp_mask(const struct sfc_mae_field_locator *field_locators, + unsigned int nb_field_locators, void *mask_ptr, + size_t mask_size) +{ + unsigned int i; + + memset(mask_ptr, 0, mask_size); + + for (i = 0; i < nb_field_locators; ++i) { + const struct sfc_mae_field_locator *fl = &field_locators[i]; + + SFC_ASSERT(fl->ofst + fl->size <= mask_size); + memset(RTE_PTR_ADD(mask_ptr, fl->ofst), 0xff, fl->size); + } +} + +static int +sfc_mae_parse_item(const struct sfc_mae_field_locator *field_locators, + unsigned int nb_field_locators, const uint8_t *spec, + const uint8_t *mask, efx_mae_match_spec_t *efx_spec, + struct rte_flow_error *error) +{ + unsigned int i; + int rc = 0; + + for (i = 0; i < nb_field_locators; ++i) { + const struct sfc_mae_field_locator *fl = &field_locators[i]; + + rc = efx_mae_match_spec_field_set(efx_spec, fl->field_id, + fl->size, spec + fl->ofst, + fl->size, mask + fl->ofst); + if (rc != 0) + break; + } + + if (rc != 0) { + rc = rte_flow_error_set(error, rc, RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "Failed to process item fields"); + } + + return rc; +} + +static const struct sfc_mae_field_locator flocs_eth[] = { + { + EFX_MAE_FIELD_ETHER_TYPE_BE, + RTE_SIZEOF_FIELD(struct rte_flow_item_eth, type), + offsetof(struct rte_flow_item_eth, type), + }, + { + EFX_MAE_FIELD_ETH_DADDR_BE, + RTE_SIZEOF_FIELD(struct rte_flow_item_eth, dst), + offsetof(struct rte_flow_item_eth, dst), + }, + { + EFX_MAE_FIELD_ETH_SADDR_BE, + RTE_SIZEOF_FIELD(struct rte_flow_item_eth, src), + offsetof(struct rte_flow_item_eth, src), + }, +}; + +static int +sfc_mae_rule_parse_item_eth(const struct rte_flow_item *item, + struct sfc_flow_parse_ctx *ctx, + struct rte_flow_error *error) +{ + struct sfc_mae_parse_ctx *ctx_mae = ctx->mae; + struct rte_flow_item_eth supp_mask; + const uint8_t *spec = NULL; + const uint8_t *mask = NULL; + int rc; + + sfc_mae_item_build_supp_mask(flocs_eth, RTE_DIM(flocs_eth), + &supp_mask, sizeof(supp_mask)); + + rc = sfc_flow_parse_init(item, + (const void **)&spec, (const void **)&mask, + (const void *)&supp_mask, + &rte_flow_item_eth_mask, + sizeof(struct rte_flow_item_eth), error); + if (rc != 0) + return rc; + + /* If "spec" is not set, could be any Ethernet */ + if (spec == NULL) + return 0; + + return sfc_mae_parse_item(flocs_eth, RTE_DIM(flocs_eth), spec, mask, + ctx_mae->match_spec_action, error); +} + static const struct sfc_flow_item sfc_flow_items[] = { { .type = RTE_FLOW_ITEM_TYPE_PHY_PORT, @@ -233,6 +332,13 @@ static const struct sfc_flow_item sfc_flow_items[] = { .ctx_type = SFC_FLOW_PARSE_CTX_MAE, .parse = sfc_mae_rule_parse_item_phy_port, }, + { + .type = RTE_FLOW_ITEM_TYPE_ETH, + .prev_layer = SFC_FLOW_ITEM_START_LAYER, + .layer = SFC_FLOW_ITEM_L2, + .ctx_type = SFC_FLOW_PARSE_CTX_MAE, + .parse = sfc_mae_rule_parse_item_eth, + }, }; int -- 2.17.1