From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8793AA04DD; Thu, 22 Oct 2020 17:51:41 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DD519AC47; Thu, 22 Oct 2020 17:51:39 +0200 (CEST) Received: from out0-153.mail.aliyun.com (out0-153.mail.aliyun.com [140.205.0.153]) by dpdk.org (Postfix) with ESMTP id 60C7FAC47 for ; Thu, 22 Oct 2020 17:51:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alibaba-inc.com; s=default; t=1603381892; h=From:To:Subject:Date:Message-Id; bh=1JM/jk6RbtfOQuGqcSekZWgloDvAQa8k2ivNpPLz7Yk=; b=p8QzHX/5l4/z1OABl3xZvydANFYMwRmlkeGPHUhzIHGh0Td8I2DHnDPihYwqt/ETTV4DIyADS8IqS1NMNzvRrVPuPXvMm/gf/Q2c289lBF4tP9o4OWPy+vFdt0nspTLxMowulhJIXMu1yAGhrY+Y34VwDa2iLAt3eduaKEpTZMA= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018047187; MF=huawei.xhw@alibaba-inc.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---.In.51nB_1603381889; Received: from rs3a10040.et2sqa.z1.et2sqa.tbsite.net(mailfrom:huawei.xhw@alibaba-inc.com fp:SMTPD_---.In.51nB_1603381889) by smtp.aliyun-inc.com(127.0.0.1); Thu, 22 Oct 2020 23:51:31 +0800 From: "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" To: ferruh.yigit@intel.com Cc: , , , , , , , "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" Date: Thu, 22 Oct 2020 23:51:22 +0800 Message-Id: <1603381885-88819-1-git-send-email-huawei.xhw@alibaba-inc.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <68ecd941-9c56-4de7-fae2-2ad15bdfd81a@alibaba-inc.com> References: <68ecd941-9c56-4de7-fae2-2ad15bdfd81a@alibaba-inc.com> Subject: [dpdk-dev] [PATCH v5 0/3] support both PIO and MMIO BAR for virtio PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "huawei.xhw" Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR. Kernel supports both PIO and MMIO BAR for legacy virtio-pci device. We handles different type of BAR in the similar way. In previous implementation, with igb_uio we get PIO address from igb_uio sysfs entry; with uio_pci_generic, we get PIO address from /proc/ioports. For PIO/MMIO RW, there is different path for different drivers and arch. For VFIO, PIO/MMIO RW is through syscall, which has big performance issue. On X86, it assumes only PIO is supported. All of the above is too much twisted. This patch unifies the way to get both PIO and MMIO address for different driver and arch, all from standard resource attr under pci sysfs. We distinguish PIO and MMIO by their address like how kernel does. It is ugly but works. v2 changes: - add more explanation in the commit message v3 changes: - fix patch format issues v4 changes: - fixes for RTE_KDRV_UIO_GENERIC -> RTE_PCI_KDRV_UIO_GENERIC v5 changes: - split into three seperate patches huawei.xhw (3): PCI: use PCI standard sysfs entry to get PIO address PCI: support MMIO in rte_pci_ioport_map/unap/read/write PCI: don't use vfio ioctl call to access PIO resource drivers/bus/pci/linux/pci.c | 89 +------------------- drivers/bus/pci/linux/pci_uio.c | 177 ++++++++++++++++++++++++++++------------ 2 files changed, 128 insertions(+), 138 deletions(-) -- 1.8.3.1