From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CFA95A04DD; Thu, 22 Oct 2020 17:52:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A8981AC68; Thu, 22 Oct 2020 17:52:18 +0200 (CEST) Received: from out0-131.mail.aliyun.com (out0-131.mail.aliyun.com [140.205.0.131]) by dpdk.org (Postfix) with ESMTP id 141D4AC66 for ; Thu, 22 Oct 2020 17:52:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alibaba-inc.com; s=default; t=1603381934; h=From:To:Subject:Date:Message-Id; bh=4UHvckWd8LJfDhk3HR+Avgdl6O3/Bb9jeM3v13CyNx0=; b=ddHVqW28C+IqS5t1ilmpHEY7P1b5EZXsOYTG8dOjjzKSKGPwnC15Y/bNJityknESqLdYIZXu1s93PcVGMJelS9ihLMdLN61JHXTBUoTA1um1N0ZrD+teikGHkSoK+Jxmif+zcob0ukw7g93ryGeIECblPpKld7P8Hp+cgSWkV5M= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R801e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018047206; MF=huawei.xhw@alibaba-inc.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---.In.51nB_1603381889; Received: from rs3a10040.et2sqa.z1.et2sqa.tbsite.net(mailfrom:huawei.xhw@alibaba-inc.com fp:SMTPD_---.In.51nB_1603381889) by smtp.aliyun-inc.com(127.0.0.1); Thu, 22 Oct 2020 23:51:32 +0800 From: "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" To: ferruh.yigit@intel.com Cc: , , , , , , , "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" Date: Thu, 22 Oct 2020 23:51:24 +0800 Message-Id: <1603381885-88819-3-git-send-email-huawei.xhw@alibaba-inc.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1603381885-88819-1-git-send-email-huawei.xhw@alibaba-inc.com> References: <68ecd941-9c56-4de7-fae2-2ad15bdfd81a@alibaba-inc.com> <1603381885-88819-1-git-send-email-huawei.xhw@alibaba-inc.com> Subject: [dpdk-dev] [PATCH v5 2/3] PCI: support MMIO in rte_pci_ioport_map/unap/read/write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "huawei.xhw" If IO BAR, we get PIO address. If MMIO BAR, we get mapped virtual address. We distinguish PIO and MMIO by their address like how kernel does. ioread/write8/16/32 is provided to access PIO/MMIO. BTW, for virtio on arch other than x86, BAR flag indicates PIO but is mapped. Signed-off-by: huawei.xhw --- drivers/bus/pci/linux/pci.c | 4 -- drivers/bus/pci/linux/pci_uio.c | 123 ++++++++++++++++++++++++++-------------- 2 files changed, 82 insertions(+), 45 deletions(-) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index 0f38abf..0dc99e9 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -715,8 +715,6 @@ int rte_pci_write_config(const struct rte_pci_device *device, break; #endif case RTE_PCI_KDRV_IGB_UIO: - pci_uio_ioport_read(p, data, len, offset); - break; case RTE_PCI_KDRV_UIO_GENERIC: pci_uio_ioport_read(p, data, len, offset); break; @@ -736,8 +734,6 @@ int rte_pci_write_config(const struct rte_pci_device *device, break; #endif case RTE_PCI_KDRV_IGB_UIO: - pci_uio_ioport_write(p, data, len, offset); - break; case RTE_PCI_KDRV_UIO_GENERIC: pci_uio_ioport_write(p, data, len, offset); break; diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c index 01f2a40..c19382f 100644 --- a/drivers/bus/pci/linux/pci_uio.c +++ b/drivers/bus/pci/linux/pci_uio.c @@ -379,14 +379,9 @@ char buf[BUFSIZ]; uint64_t phys_addr, end_addr, flags; unsigned long base; + bool iobar; int i; - if (rte_eal_iopl_init() != 0) { - RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for PCI device %s\n", - __func__, dev->name); - return -1; - } - /* open and read addresses of the corresponding resource in sysfs */ snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource", rte_pci_get_sysfs_path(), dev->addr.domain, dev->addr.bus, @@ -408,15 +403,30 @@ &end_addr, &flags) < 0) goto error; - if (!(flags & IORESOURCE_IO)) { - RTE_LOG(ERR, EAL, "%s(): bar resource other than IO is not supported\n", __func__); + if (flags & IORESOURCE_IO) { + iobar = 1; + base = (unsigned long)phys_addr; + RTE_LOG(INFO, EAL, "%s(): PIO BAR %08lx detected\n", __func__, base); + } else if (flags & IORESOURCE_MEM) { + iobar = 0; + base = (unsigned long)dev->mem_resource[bar].addr; + RTE_LOG(INFO, EAL, "%s(): MMIO BAR %08lx detected\n", __func__, base); + } else { + RTE_LOG(ERR, EAL, "%s(): unknown BAR type\n", __func__); + goto error; + } + + + if (iobar && rte_eal_iopl_init() != 0) { + RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for PCI device %s\n", + __func__, dev->name); goto error; } - base = (unsigned long)phys_addr; - RTE_LOG(INFO, EAL, "%s(): PIO BAR %08lx detected\n", __func__, base); - if (base > UINT16_MAX) + if (iobar && (base > UINT16_MAX)) { + RTE_LOG(ERR, EAL, "%s(): %08lx too large PIO resource\n", __func__, base); goto error; + } /* FIXME only for primary process ? */ if (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) { @@ -517,6 +527,61 @@ } #endif +#define PIO_MAX 0x10000 +static inline uint8_t ioread8(void *addr) +{ + uint8_t val; + + val = (uint64_t)(uintptr_t)addr >= PIO_MAX ? + *(volatile uint8_t *)addr : + inb((unsigned long)addr); + + return val; +} + +static inline uint16_t ioread16(void *addr) +{ + uint16_t val; + + val = (uint64_t)(uintptr_t)addr >= PIO_MAX ? + *(volatile uint16_t *)addr : + inw((unsigned long)addr); + + return val; +} + +static inline uint32_t ioread32(void *addr) +{ + uint32_t val; + + val = (uint64_t)(uintptr_t)addr >= PIO_MAX ? + *(volatile uint32_t *)addr : + inl((unsigned long)addr); + + return val; +} + +static inline void iowrite8(uint8_t val, void *addr) +{ + (uint64_t)(uintptr_t)addr >= PIO_MAX ? + *(volatile uint8_t *)addr = val : + outb(val, (unsigned long)addr); +} + +static inline void iowrite16(uint16_t val, void *addr) +{ + (uint64_t)(uintptr_t)addr >= PIO_MAX ? + *(volatile uint16_t *)addr = val : + outw(val, (unsigned long)addr); +} + +static inline void iowrite32(uint32_t val, void *addr) +{ + (uint64_t)(uintptr_t)addr >= PIO_MAX ? + *(volatile uint32_t *)addr = val : + outl(val, (unsigned long)addr); +} + void pci_uio_ioport_read(struct rte_pci_ioport *p, void *data, size_t len, off_t offset) @@ -528,25 +593,13 @@ for (d = data; len > 0; d += size, reg += size, len -= size) { if (len >= 4) { size = 4; -#if defined(RTE_ARCH_X86) - *(uint32_t *)d = inl(reg); -#else - *(uint32_t *)d = *(volatile uint32_t *)reg; -#endif + *(uint32_t *)d = ioread32((void *)reg); } else if (len >= 2) { size = 2; -#if defined(RTE_ARCH_X86) - *(uint16_t *)d = inw(reg); -#else - *(uint16_t *)d = *(volatile uint16_t *)reg; -#endif + *(uint16_t *)d = ioread16((void *)reg); } else { size = 1; -#if defined(RTE_ARCH_X86) - *d = inb(reg); -#else - *d = *(volatile uint8_t *)reg; -#endif + *d = ioread8((void *)reg); } } } @@ -562,25 +615,13 @@ for (s = data; len > 0; s += size, reg += size, len -= size) { if (len >= 4) { size = 4; -#if defined(RTE_ARCH_X86) - outl_p(*(const uint32_t *)s, reg); -#else - *(volatile uint32_t *)reg = *(const uint32_t *)s; -#endif + iowrite32(*(const uint32_t *)s, (void *)reg); } else if (len >= 2) { size = 2; -#if defined(RTE_ARCH_X86) - outw_p(*(const uint16_t *)s, reg); -#else - *(volatile uint16_t *)reg = *(const uint16_t *)s; -#endif + iowrite16(*(const uint16_t *)s, (void *)reg); } else { size = 1; -#if defined(RTE_ARCH_X86) - outb_p(*s, reg); -#else - *(volatile uint8_t *)reg = *s; -#endif + iowrite8(*s, (void *)reg); } } } -- 1.8.3.1