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From: Liang Ma <liang.j.ma@intel.com>
To: dev@dpdk.org
Cc: anatoly.burakov@intel.com, jia.guo@intel.com, haiyue.wang@intel.com,
bruce.richardson@intel.com, konstantin.ananyev@intel.com,
david.hunt@intel.com, jerinjacobk@gmail.com, thomas@monjalon.net,
timothy.mcdaniel@intel.com, gage.eads@intel.com,
Liang Ma <liang.j.ma@intel.com>
Date: Fri, 23 Oct 2020 18:26:02 +0100
Message-Id: <1603473962-15286-1-git-send-email-liang.j.ma@intel.com>
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References: <da3fe4e5bbe976882c56a71d20a9055c1600e6aa.1602763439.git.anatoly.burakov@intel.com>
Subject: [dpdk-dev] [PATCH v8 06/10] net/ixgbe: implement power management
API
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Implement support for the power management API by implementing a
`get_wake_addr` function that will return an address of an RX ring's
status bit.
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Signed-off-by: Liang Ma <liang.j.ma@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
---
drivers/net/ixgbe/ixgbe_ethdev.c | 1 +
drivers/net/ixgbe/ixgbe_rxtx.c | 25 +++++++++++++++++++++++++
drivers/net/ixgbe/ixgbe_rxtx.h | 2 ++
3 files changed, 28 insertions(+)
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 00101c2eec..fcc4026372 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -588,6 +588,7 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
.udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
.tm_ops_get = ixgbe_tm_ops_get,
.tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
+ .get_wake_addr = ixgbe_get_wake_addr,
};
/*
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index d1d3baff90..096dff37ba 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -1367,6 +1367,31 @@ const uint32_t
RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
};
+int ixgbe_get_wake_addr(void *rx_queue, volatile void **tail_desc_addr,
+ uint64_t *expected, uint64_t *mask, uint8_t *data_sz)
+{
+ volatile union ixgbe_adv_rx_desc *rxdp;
+ struct ixgbe_rx_queue *rxq = rx_queue;
+ uint16_t desc;
+
+ desc = rxq->rx_tail;
+ rxdp = &rxq->rx_ring[desc];
+ /* watch for changes in status bit */
+ *tail_desc_addr = &rxdp->wb.upper.status_error;
+
+ /*
+ * we expect the DD bit to be set to 1 if this descriptor was already
+ * written to.
+ */
+ *expected = rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD);
+ *mask = rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD);
+
+ /* the registers are 32-bit */
+ *data_sz = 4;
+
+ return 0;
+}
+
/* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
static inline uint32_t
ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h
index 6d2f7c9da3..1ef0b05e66 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.h
+++ b/drivers/net/ixgbe/ixgbe_rxtx.h
@@ -299,5 +299,7 @@ uint64_t ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev);
uint64_t ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev);
uint64_t ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev);
uint64_t ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev);
+int ixgbe_get_wake_addr(void *rx_queue, volatile void **tail_desc_addr,
+ uint64_t *expected, uint64_t *mask, uint8_t *data_sz);
#endif /* _IXGBE_RXTX_H_ */
--
2.17.1