From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8855DA04E7; Sun, 1 Nov 2020 18:59:39 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CE4E12DCC; Sun, 1 Nov 2020 18:58:49 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 4E3982BAA for ; Sun, 1 Nov 2020 18:58:48 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from matan@nvidia.com) with SMTP; 1 Nov 2020 19:58:46 +0200 Received: from nvidia.com (pegasus25.mtr.labs.mlnx [10.210.16.10]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0A1Hvxnu009671; Sun, 1 Nov 2020 19:58:46 +0200 From: Matan Azrad To: Viacheslav Ovsiienko Cc: dev@dpdk.org, Dekel Peled Date: Sun, 1 Nov 2020 17:57:48 +0000 Message-Id: <1604253472-213766-6-git-send-email-matan@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1604253472-213766-1-git-send-email-matan@nvidia.com> References: <1604008681-414157-1-git-send-email-matan@nvidia.com> <1604253472-213766-1-git-send-email-matan@nvidia.com> Subject: [dpdk-dev] [PATCH v2 5/9] common/mlx5: add definitions for ASO flow hit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled This patch adds different PRM definitions, related to ASO flow hit feature, in MLX5 PMD code. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/linux/meson.build | 2 ++ drivers/common/mlx5/mlx5_prm.h | 66 ++++++++++++++++++++++++++++++++++- 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 7ffb142..87f7bfd 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -126,6 +126,8 @@ has_sym_args = [ 'MLX5_OPCODE_SEND_EN' ], [ 'HAVE_MLX5_OPCODE_WAIT', 'infiniband/mlx5dv.h', 'MLX5_OPCODE_WAIT' ], + [ 'HAVE_MLX5_OPCODE_ACCESS_ASO', 'infiniband/mlx5dv.h', + 'MLX5_OPCODE_ACCESS_ASO' ], [ 'HAVE_SUPPORTED_40000baseKR4_Full', 'linux/ethtool.h', 'SUPPORTED_40000baseKR4_Full' ], [ 'HAVE_SUPPORTED_40000baseCR4_Full', 'linux/ethtool.h', diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2c5da16..7394356 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -120,7 +120,7 @@ MLX5_WQE_DSEG_SIZE + \ MLX5_ESEG_MIN_INLINE_SIZE) -/* Missed in mlv5dv.h, should define here. */ +/* Missed in mlx5dv.h, should define here. */ #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW #define MLX5_OPCODE_ENHANCED_MPSW 0x29u #endif @@ -133,6 +133,10 @@ #define MLX5_OPCODE_WAIT 0x0fu #endif +#ifndef HAVE_MLX5_OPCODE_ACCESS_ASO +#define MLX5_OPCODE_ACCESS_ASO 0x2du +#endif + /* CQE value to inform that VLAN is stripped. */ #define MLX5_CQE_VLAN_STRIPPED (1u << 0) @@ -2349,6 +2353,66 @@ struct mlx5_ifc_create_flow_hit_aso_in_bits { struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; }; +enum mlx5_access_aso_op_mod { + ASO_OP_MOD_IPSEC = 0x0, + ASO_OP_MOD_CONNECTION_TRACKING = 0x1, + ASO_OP_MOD_POLICER = 0x2, + ASO_OP_MOD_RACE_AVOIDANCE = 0x3, + ASO_OP_MOD_FLOW_HIT = 0x4, +}; + +enum mlx5_aso_data_mask_mode { + BITWISE_64BIT = 0x0, + BYTEWISE_64BYTE = 0x1, + CALCULATED_64BYTE = 0x2, +}; + +enum mlx5_aso_pre_cond_op { + ASO_OP_ALWAYS_FALSE = 0x0, + ASO_OP_ALWAYS_TRUE = 0x1, + ASO_OP_EQUAL = 0x2, + ASO_OP_NOT_EQUAL = 0x3, + ASO_OP_GREATER_OR_EQUAL = 0x4, + ASO_OP_LESSER_OR_EQUAL = 0x5, + ASO_OP_LESSER = 0x6, + ASO_OP_GREATER = 0x7, + ASO_OP_CYCLIC_GREATER = 0x8, + ASO_OP_CYCLIC_LESSER = 0x9, +}; + +enum mlx5_aso_op { + ASO_OPER_LOGICAL_AND = 0x0, + ASO_OPER_LOGICAL_OR = 0x1, +}; + +/* ASO WQE CTRL segment. */ +struct mlx5_aso_cseg { + uint32_t va_h; + uint32_t va_l_ro; + uint32_t lkey; + uint32_t operand_masks; + uint32_t condition_0_data; + uint32_t condition_0_mask; + uint32_t condition_1_data; + uint32_t condition_1_mask; + uint64_t bitwise_data; + uint64_t data_mask; +} __rte_packed; + +#define MLX5_ASO_WQE_DSEG_SIZE 0x40 + +/* ASO WQE Data segment. */ +struct mlx5_aso_dseg { + uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; +} __rte_packed; + +/* ASO WQE. */ +struct mlx5_aso_wqe { + struct mlx5_wqe_cseg general_cseg; + struct mlx5_aso_cseg aso_cseg; + struct mlx5_aso_dseg aso_dseg; +} __rte_packed; + enum { MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, }; -- 1.8.3.1