From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22982A04E7; Mon, 2 Nov 2020 15:40:02 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 421C7C958; Mon, 2 Nov 2020 15:38:07 +0100 (CET) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by dpdk.org (Postfix) with ESMTP id E8E34C91A for ; Mon, 2 Nov 2020 15:37:59 +0100 (CET) Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4CPwW66bLfzLsmd for ; Mon, 2 Nov 2020 22:37:54 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Mon, 2 Nov 2020 22:37:47 +0800 From: Lijun Ou To: CC: , Date: Mon, 2 Nov 2020 22:38:17 +0800 Message-ID: <1604327899-60126-7-git-send-email-oulijun@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604327899-60126-1-git-send-email-oulijun@huawei.com> References: <1604327899-60126-1-git-send-email-oulijun@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 6/8] net/hns3: fix visit unsupported QL register error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng If hardware does not support QL(quantity limiter), the int_ql_max is 0, software should confirm ql_value is less than int_ql_max before write QL register. This patch add check of int_ql_max value from firmware and delete the unused variable coalesce_mode. Fixes: 27911a6e62e5 ("net/hns3: add Rx interrupts compatibility") Cc: stable@dpdk.org Signed-off-by: Hongbo Zheng Signed-off-by: Lijun Ou --- drivers/net/hns3/hns3_ethdev.c | 8 ++++++-- drivers/net/hns3/hns3_ethdev.h | 22 ++++------------------ drivers/net/hns3/hns3_ethdev_vf.c | 8 ++++++-- drivers/net/hns3/hns3_rxtx.c | 7 ++++++- 4 files changed, 22 insertions(+), 23 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 1e382f1..180b313 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2291,6 +2291,10 @@ hns3_init_ring_with_vector(struct hns3_hw *hw) hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, HNS3_TQP_INTR_GL_DEFAULT); hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); + /* + * QL(quantity limiter) is not used currently, just set 0 to + * close it. + */ hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); ret = hns3_bind_ring_with_vector(hw, vec, false, @@ -2952,6 +2956,7 @@ hns3_set_default_dev_specifications(struct hns3_hw *hw) hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; hw->rss_key_size = HNS3_RSS_KEY_SIZE; hw->max_tm_rate = HNS3_ETHER_MAX_RATE; + hw->intr.int_ql_max = HNS3_INTR_QL_NONE; } static void @@ -2965,6 +2970,7 @@ hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); + hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); } static int @@ -3031,7 +3037,6 @@ hns3_get_capability(struct hns3_hw *hw) if (revision < PCI_REVISION_ID_HIP09_A) { hns3_set_default_dev_specifications(hw); hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; - hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; @@ -3050,7 +3055,6 @@ hns3_get_capability(struct hns3_hw *hw) } hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; - hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index a2b61ff..531a6cb 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -379,12 +379,11 @@ struct hns3_reset_data { #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 #define HNS3_INTR_MAPPING_VEC_ALL 1 -#define HNS3_INTR_COALESCE_NON_QL 0 -#define HNS3_INTR_COALESCE_QL 1 - #define HNS3_INTR_COALESCE_GL_UINT_2US 0 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 +#define HNS3_INTR_QL_NONE 0 + struct hns3_queue_intr { /* * interrupt mapping mode. @@ -406,27 +405,14 @@ struct hns3_queue_intr { */ uint8_t mapping_mode; /* - * interrupt coalesce mode. - * value range: - * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL - * - * - HNS3_INTR_COALESCE_NON_QL - * For some versions of hardware network engine, hardware doesn't - * support QL(quanity limiter) algorithm for interrupt coalesce - * of queue's interrupt. - * - * - HNS3_INTR_COALESCE_QL - * In this mode, hardware support QL(quanity limiter) algorithm for - * interrupt coalesce of queue's interrupt. - */ - uint8_t coalesce_mode; - /* * The unit of GL(gap limiter) configuration for interrupt coalesce of * queue's interrupt. * value range: * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US */ uint8_t gl_unit; + /* The max QL(quantity limiter) value */ + uint16_t int_ql_max; }; #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index c903e07..088a46f 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -757,6 +757,10 @@ hns3vf_init_ring_with_vector(struct hns3_hw *hw) hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, HNS3_TQP_INTR_GL_DEFAULT); hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); + /* + * QL(quantity limiter) is not used currently, just set 0 to + * close it. + */ hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); ret = hns3vf_bind_ring_with_vector(hw, vec, false, @@ -1149,6 +1153,7 @@ hns3vf_set_default_dev_specifications(struct hns3_hw *hw) hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; hw->rss_key_size = HNS3_RSS_KEY_SIZE; + hw->intr.int_ql_max = HNS3_INTR_QL_NONE; } static void @@ -1161,6 +1166,7 @@ hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); + hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); } static int @@ -1210,7 +1216,6 @@ hns3vf_get_capability(struct hns3_hw *hw) if (revision < PCI_REVISION_ID_HIP09_A) { hns3vf_set_default_dev_specifications(hw); hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; - hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; @@ -1228,7 +1233,6 @@ hns3vf_get_capability(struct hns3_hw *hw) } hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; - hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index c82116d..afb1e7d 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -851,7 +851,12 @@ hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value) { uint32_t addr; - if (hw->intr.coalesce_mode == HNS3_INTR_COALESCE_NON_QL) + /* + * int_ql_max == 0 means the hardware does not support QL, + * QL regs config is not permitted if QL is not supported, + * here just return. + */ + if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE) return; addr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE; -- 2.7.4