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From: Bing Zhao <bingz@nvidia.com>
To: viacheslavo@nvidia.com, matan@nvidia.com
Cc: dev@dpdk.org, orika@nvidia.com, rasland@nvidia.com, stable@dpdk.org
Subject: [dpdk-dev] [PATCH] net/mlx5: fix the eCPRI common header endianness
Date: Tue,  3 Nov 2020 13:41:58 +0800
Message-ID: <1604382118-336293-1-git-send-email-bingz@nvidia.com> (raw)

The input header of a RTE flow item is with network byte order. In
the host with little endian, the bit field order are the same as the
byte order.
When checking the an eCPRI message type, the wrong field will be
selected. Right now, since the whole u32 is being checked and for
all types, the following implementation is unique. There is no
functional risk but it is still an error to fix.

Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")

Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
 drivers/net/mlx5/mlx5_flow_dv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 01b6e7c..7af01e9 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7798,6 +7798,7 @@ struct mlx5_hlist_entry *
 	struct mlx5_priv *priv = dev->data->dev_private;
 	const struct rte_flow_item_ecpri *ecpri_m = item->mask;
 	const struct rte_flow_item_ecpri *ecpri_v = item->spec;
+	struct rte_ecpri_common_hdr common;
 	void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
 	void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
@@ -7838,7 +7839,8 @@ struct mlx5_hlist_entry *
 	 * Some wildcard rules only matching type field should be supported.
 	if (ecpri_m->hdr.dummy[0]) {
-		switch (ecpri_v->hdr.common.type) {
+		common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
+		switch (common.type) {

             reply	other threads:[~2020-11-03  5:42 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03  5:41 Bing Zhao [this message]
2020-11-05 15:01 ` Raslan Darawsheh
2020-11-06 11:19 ` Ferruh Yigit
2020-11-06 14:10   ` Bing Zhao
2020-11-06 17:41     ` Ferruh Yigit
2020-11-09  6:01       ` Bing Zhao

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