From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D3B6A0521; Tue, 3 Nov 2020 06:42:10 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ED1B3BC62; Tue, 3 Nov 2020 06:42:08 +0100 (CET) Received: from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130]) by dpdk.org (Postfix) with ESMTP id 67B12A54B; Tue, 3 Nov 2020 06:42:06 +0100 (CET) From: Bing Zhao To: viacheslavo@nvidia.com, matan@nvidia.com Cc: dev@dpdk.org, orika@nvidia.com, rasland@nvidia.com, stable@dpdk.org Date: Tue, 3 Nov 2020 13:41:58 +0800 Message-Id: <1604382118-336293-1-git-send-email-bingz@nvidia.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH] net/mlx5: fix the eCPRI common header endianness X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The input header of a RTE flow item is with network byte order. In the host with little endian, the bit field order are the same as the byte order. When checking the an eCPRI message type, the wrong field will be selected. Right now, since the whole u32 is being checked and for all types, the following implementation is unique. There is no functional risk but it is still an error to fix. Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header") Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 01b6e7c..7af01e9 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7798,6 +7798,7 @@ struct mlx5_hlist_entry * struct mlx5_priv *priv = dev->data->dev_private; const struct rte_flow_item_ecpri *ecpri_m = item->mask; const struct rte_flow_item_ecpri *ecpri_v = item->spec; + struct rte_ecpri_common_hdr common; void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_4); void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4); @@ -7838,7 +7839,8 @@ struct mlx5_hlist_entry * * Some wildcard rules only matching type field should be supported. */ if (ecpri_m->hdr.dummy[0]) { - switch (ecpri_v->hdr.common.type) { + common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32); + switch (common.type) { case RTE_ECPRI_MSG_TYPE_IQ_DATA: case RTE_ECPRI_MSG_TYPE_RTC_CTRL: case RTE_ECPRI_MSG_TYPE_DLY_MSR: -- 1.8.3.1