From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2D6B8A04DD; Thu, 5 Nov 2020 15:01:40 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 24FDBC882; Thu, 5 Nov 2020 14:59:46 +0100 (CET) Received: from lb.pantheon.sk (lb.pantheon.sk [46.229.239.20]) by dpdk.org (Postfix) with ESMTP id 4B09AC86A for ; Thu, 5 Nov 2020 14:59:41 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by lb.pantheon.sk (Postfix) with ESMTP id AC581B6B64; Thu, 5 Nov 2020 14:59:37 +0100 (CET) X-Virus-Scanned: amavisd-new at siecit.sk Received: from lb.pantheon.sk ([127.0.0.1]) by localhost (lb.pantheon.sk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q-7AZRYqVLK9; Thu, 5 Nov 2020 14:59:35 +0100 (CET) Received: from service-node1.lab.pantheon.local (unknown [46.229.239.141]) by lb.pantheon.sk (Postfix) with ESMTP id A3C65B6B5E; Thu, 5 Nov 2020 14:59:31 +0100 (CET) From: =?UTF-8?q?Juraj=20Linke=C5=A1?= To: bruce.richardson@intel.com, Ruifeng.Wang@arm.com, Honnappa.Nagarahalli@arm.com, Phil.Yang@arm.com, vcchunga@amazon.com, Dharmik.Thakkar@arm.com, jerinjacobk@gmail.com, hemant.agrawal@nxp.com, ajit.khaparde@broadcom.com, ferruh.yigit@intel.com, aconole@redhat.com Cc: dev@dpdk.org, =?UTF-8?q?Juraj=20Linke=C5=A1?= Date: Thu, 5 Nov 2020 14:59:12 +0100 Message-Id: <1604584762-25321-5-git-send-email-juraj.linkes@pantheon.tech> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604584762-25321-1-git-send-email-juraj.linkes@pantheon.tech> References: <1604323278-18039-1-git-send-email-juraj.linkes@pantheon.tech> <1604584762-25321-1-git-send-email-juraj.linkes@pantheon.tech> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v7 04/14] build: reformat and move Arm config and comments X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Change formatting so that it's more consistent and readable, add/modify comments/stdout messages, move configuration options to more appropriate places and make the order consistent according to these rules: 1. First list generic configuration options, then list options that may be overwritten. List SoC-specific options last. 2. For SoC-specific options, list number of cores before the number of NUMA nodes, to make it consistent with config/meson.build. Signed-off-by: Juraj Linkeš --- config/arm/arm64_armv8_linux_gcc | 21 ++++++- config/arm/meson.build | 94 +++++++++++++++++++------------- 2 files changed, 77 insertions(+), 38 deletions(-) diff --git a/config/arm/arm64_armv8_linux_gcc b/config/arm/arm64_armv8_linux_gcc index 13ee8b223..04cd82ba9 100644 --- a/config/arm/arm64_armv8_linux_gcc +++ b/config/arm/arm64_armv8_linux_gcc @@ -13,9 +13,16 @@ cpu = 'armv8-a' endian = 'little' [properties] +# Supported implementers: +# 'generic': Generic armv8 +# '0x41': Arm +# '0x43': Cavium +# '0x50': Ampere Computing +# '0x56': Marvell ARMADA +# 'dpaa': NXP DPAA implementer_id = 'generic' -# Valid options for Arm's part_number: +# Supported part_numbers for generic, 0x41, 0x56, dpaa: # 'generic': valid for all armv8-a architectures (default value) # '0xd03': cortex-a53 # '0xd04': cortex-a35 @@ -25,4 +32,16 @@ implementer_id = 'generic' # '0xd09': cortex-a73 # '0xd0a': cortex-a75 # '0xd0b': cortex-a76 +# '0xd0c': neoverse-n1 part_number = 'generic' + +# Supported part_numbers for 0x43: +# 'generic': valid for all Cavium builds +# '0xa1': thunderxt88 +# '0xa2': thunderxt81 +# '0xa3': thunderxt83 +# '0xaf': thunderx2t99 +# '0xb2': octeontx2 + +# Supported part_numbers for 0x50: +# 'generic': valid for all Ampere builds diff --git a/config/arm/meson.build b/config/arm/meson.build index 45d1d1d79..05cc9e4f4 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -5,6 +5,7 @@ arm_force_native_march = false +# common flags to all aarch64 builds, with lowest priority flags_common_default = [ # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) # to determine the best threshold in code. Refer to notes in source file @@ -12,8 +13,8 @@ flags_common_default = [ ['RTE_ARCH_ARM64_MEMCPY', false], # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048], # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512], - # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're - # strong reasons. + # Leave below RTE_ARM64_MEMCPY_xxx options commented out, + # unless there are strong reasons. # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false], # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], @@ -24,69 +25,86 @@ flags_common_default = [ ['RTE_SCHED_VECTOR', false], ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], + ['RTE_CACHE_LINE_SIZE', 128] ] +# implementer specific aarch64 flags, with middle priority +# (will overwrite common flags) flags_implementer_generic = [ ['RTE_MACHINE', '"armv8a"'], - ['RTE_MAX_LCORE', 256], ['RTE_USE_C11_MEM_MODEL', true], - ['RTE_CACHE_LINE_SIZE', 128]] + ['RTE_CACHE_LINE_SIZE', 128], + ['RTE_MAX_LCORE', 256] +] flags_implementer_arm = [ ['RTE_MACHINE', '"armv8a"'], - ['RTE_MAX_LCORE', 16], ['RTE_USE_C11_MEM_MODEL', true], - ['RTE_CACHE_LINE_SIZE', 64]] + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_LCORE', 16] +] flags_implementer_cavium = [ + ['RTE_MAX_VFIO_GROUPS', 128], ['RTE_CACHE_LINE_SIZE', 128], - ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128]] + ['RTE_MAX_NUMA_NODES', 2] +] flags_implementer_dpaa = [ ['RTE_MACHINE', '"dpaa"'], + ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false], ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], - ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] + ['RTE_MAX_NUMA_NODES', 1] +] flags_implementer_emag = [ ['RTE_MACHINE', '"emag"'], ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_NUMA_NODES', 1], - ['RTE_MAX_LCORE', 32]] + ['RTE_MAX_LCORE', 32], + ['RTE_MAX_NUMA_NODES', 1] +] flags_implementer_armada = [ ['RTE_MACHINE', '"armv8a"'], ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_NUMA_NODES', 1], - ['RTE_MAX_LCORE', 16]] + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] +] +# part number specific aarch64 flags, with highest priority +# (will overwrite both common and implementer specific flags) flags_part_number_thunderx = [ ['RTE_MACHINE', '"thunderx"'], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_USE_C11_MEM_MODEL', false] +] flags_part_number_thunderx2 = [ ['RTE_MACHINE', '"thunderx2"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 256], - ['RTE_ARM_FEATURE_ATOMICS', true], - ['RTE_USE_C11_MEM_MODEL', true]] + ['RTE_MAX_NUMA_NODES', 2] +] flags_part_number_octeontx2 = [ ['RTE_MACHINE', '"octeontx2"'], - ['RTE_MAX_NUMA_NODES', 1], - ['RTE_MAX_LCORE', 36], ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_USE_C11_MEM_MODEL', true], ['RTE_EAL_IGB_UIO', false], - ['RTE_USE_C11_MEM_MODEL', true]] + ['RTE_MAX_LCORE', 36], + ['RTE_MAX_NUMA_NODES', 1] +] flags_part_number_n1generic = [ ['RTE_MACHINE', '"neoverse-n1"'], - ['RTE_MAX_LCORE', 64], - ['RTE_CACHE_LINE_SIZE', 64], ['RTE_ARM_FEATURE_ATOMICS', true], ['RTE_USE_C11_MEM_MODEL', true], - ['RTE_MAX_MEM_MB', 1048576], - ['RTE_MAX_NUMA_NODES', 1], ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], - ['RTE_LIBRTE_VHOST_NUMA', false]] + ['RTE_LIBRTE_VHOST_NUMA', false], + ['RTE_MAX_MEM_MB', 1048576], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 1] +] +# arm config (implementer 0x41) is the default config part_number_config_arm = [ ['generic', ['-march=armv8-a+crc', '-moutline-atomics']], ['native', ['-march=native']], @@ -97,8 +115,8 @@ part_number_config_arm = [ ['0xd09', ['-mcpu=cortex-a73']], ['0xd0a', ['-mcpu=cortex-a75']], ['0xd0b', ['-mcpu=cortex-a76']], - ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_part_number_n1generic]] - + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_part_number_n1generic] +] part_number_config_cavium = [ ['generic', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], ['native', ['-march=native']], @@ -106,13 +124,14 @@ part_number_config_cavium = [ ['0xa2', ['-mcpu=thunderxt81'], flags_part_number_thunderx], ['0xa3', ['-mcpu=thunderxt83'], flags_part_number_thunderx], ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_part_number_thunderx2], - ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_part_number_octeontx2]] - + ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_part_number_octeontx2] +] part_number_config_emag = [ ['generic', ['-march=armv8-a+crc+crypto', '-mtune=emag']], - ['native', ['-march=native']]] + ['native', ['-march=native']] +] -## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) +## Arm implementer ID (MIDR in Arm Architecture Reference Manual) implementer_generic = ['Generic armv8', flags_implementer_generic, part_number_config_arm] implementer_0x41 = ['Arm', flags_implementer_arm, part_number_config_arm] implementer_0x43 = ['Cavium', flags_implementer_cavium, part_number_config_cavium] @@ -124,21 +143,21 @@ dpdk_conf.set('RTE_ARCH_ARM', 1) dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) if dpdk_conf.get('RTE_ARCH_32') + # armv7 build dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) dpdk_conf.set('RTE_ARCH_ARMv7', 1) # the minimum architecture supported, armv7-a, needs the following, - # mk/machine/armv7a/rte.vars.mk sets it too machine_args += '-mfpu=neon' else - dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128) - dpdk_conf.set('RTE_ARCH_ARM64', 1) - + # aarch64 build implementer_id = 'generic' machine_args = [] # Clear previous machine args if machine == 'generic' and not meson.is_cross_build() + # generic build implementer_config = implementer_generic part_number = 'generic' elif not meson.is_cross_build() + # native build # The script returns ['Implementer', 'Variant', 'Architecture', # 'Primary Part number', 'Revision'] detect_vendor = find_program(join_paths( @@ -159,6 +178,7 @@ else part_number = 'native' endif else + # cross build implementer_id = meson.get_cross_property('implementer_id', 'generic') part_number = meson.get_cross_property('part_number', 'generic') implementer_config = get_variable('implementer_' + implementer_id) @@ -195,7 +215,7 @@ else endif endforeach endif -message(machine_args) +message('Using machine args: @0@'.format(machine_args)) if (cc.get_define('__ARM_NEON', args: machine_args) != '' or cc.get_define('__aarch64__', args: machine_args) != '') -- 2.20.1