From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: dev@dpdk.org
Cc: rasland@nvidia.com, matan@nvidia.com, stable@dpdk.org
Subject: [dpdk-dev] [PATCH 2/4] regex/mlx5: fix UAR allocation
Date: Tue, 10 Nov 2020 16:04:17 +0000 [thread overview]
Message-ID: <1605024259-18318-2-git-send-email-viacheslavo@nvidia.com> (raw)
In-Reply-To: <1605024259-18318-1-git-send-email-viacheslavo@nvidia.com>
This patch provides the UAR allocation workaround for the
hosts where UAR allocation with Write-Combining memory
mapping type fails.
Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/regex/mlx5/mlx5_regex.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index 17590b9..05048e7 100644
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -176,7 +176,12 @@
rte_errno = ENOMEM;
goto error;
}
- priv->uar = mlx5_glue->devx_alloc_uar(ctx, 0);
+ /*
+ * This PMD always claims the write memory barrier on UAR
+ * registers writings, it is safe to allocate UAR with any
+ * memory mapping type.
+ */
+ priv->uar = mlx5_devx_alloc_uar(ctx, -1);
if (!priv->uar) {
DRV_LOG(ERR, "can't allocate uar.");
rte_errno = ENOMEM;
--
1.8.3.1
next prev parent reply other threads:[~2020-11-10 16:04 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-10 16:04 [dpdk-dev] [PATCH 1/4] common/mlx5: share UAR allocation routine Viacheslav Ovsiienko
2020-11-10 16:04 ` Viacheslav Ovsiienko [this message]
2020-11-10 16:04 ` [dpdk-dev] [PATCH 3/4] vdpa/mlx5: fix UAR allocation Viacheslav Ovsiienko
2020-11-10 16:04 ` [dpdk-dev] [PATCH 4/4] net/mlx5: fix UAR used by ASO queues Viacheslav Ovsiienko
2020-11-14 8:36 ` [dpdk-dev] [dpdk-stable] [PATCH 1/4] common/mlx5: share UAR allocation routine Thomas Monjalon
2020-11-14 10:01 ` Thomas Monjalon
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