From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F422DA09D9; Wed, 11 Nov 2020 21:25:37 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4CF685913; Wed, 11 Nov 2020 21:25:36 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id D567C493D for ; Wed, 11 Nov 2020 21:25:34 +0100 (CET) IronPort-SDR: Xigf36a7R5P42RRmFYnT1Muq+lNEVasa7vIHDMoEMjYWUVvh7SfBzJZfG0YcszlBFv6vIijjOP 69GIDOp5+TUw== X-IronPort-AV: E=McAfee;i="6000,8403,9802"; a="167627803" X-IronPort-AV: E=Sophos;i="5.77,470,1596524400"; d="scan'208";a="167627803" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2020 12:25:32 -0800 IronPort-SDR: 324pu8Ttc/C1WpJP4MBiHx9EOFysBJOcdWcka/xVnlUmP9/KHc+oqxR4wRtxRAGMYCCCpHsjXO u9DOt9Z15ypg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,470,1596524400"; d="scan'208";a="531855315" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by fmsmga005.fm.intel.com with ESMTP; 11 Nov 2020 12:25:29 -0800 From: Timothy McDaniel To: Cc: dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com, harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net, david.marchand@redhat.com Date: Wed, 11 Nov 2020 14:27:00 -0600 Message-Id: <1605126422-522-2-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1605126422-522-1-git-send-email-timothy.mcdaniel@intel.com> References: <1605126422-522-1-git-send-email-timothy.mcdaniel@intel.com> Subject: [dpdk-dev] [PATCH] event/dlb2: remove duplicate/unused PCI code and constants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Use rte_pci_find_ext_capability instead of private version, Remove unused PCI offsets and values Use PCI definitions from rte_pci.h, where available. Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/pf/dlb2_main.c | 46 ++++++--------------------------------- 1 file changed, 7 insertions(+), 39 deletions(-) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 06b6aee..a9d407f 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -26,17 +26,10 @@ #define NO_OWNER_VF 0 /* PF ONLY! */ #define NOT_VF_REQ false /* PF ONLY! */ -#define DLB2_PCI_CFG_SPACE_SIZE 256 #define DLB2_PCI_CAP_POINTER 0x34 #define DLB2_PCI_CAP_NEXT(hdr) (((hdr) >> 8) & 0xFC) #define DLB2_PCI_CAP_ID(hdr) ((hdr) & 0xFF) -#define DLB2_PCI_EXT_CAP_NEXT(hdr) (((hdr) >> 20) & 0xFFC) -#define DLB2_PCI_EXT_CAP_ID(hdr) ((hdr) & 0xFFFF) -#define DLB2_PCI_EXT_CAP_ID_ERR 1 -#define DLB2_PCI_ERR_UNCOR_MASK 8 -#define DLB2_PCI_ERR_UNC_UNSUP 0x00100000 -#define DLB2_PCI_EXP_DEVCTL 8 #define DLB2_PCI_LNKCTL 16 #define DLB2_PCI_SLTCTL 24 #define DLB2_PCI_RTCTL 28 @@ -44,14 +37,12 @@ #define DLB2_PCI_LNKCTL2 48 #define DLB2_PCI_SLTCTL2 56 #define DLB2_PCI_CMD 4 -#define DLB2_PCI_X_CMD 2 #define DLB2_PCI_EXP_DEVSTA 10 #define DLB2_PCI_EXP_DEVSTA_TRPND 0x20 #define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000 #define DLB2_PCI_CAP_ID_EXP 0x10 #define DLB2_PCI_CAP_ID_MSIX 0x11 -#define DLB2_PCI_EXT_CAP_ID_PAS 0x1B #define DLB2_PCI_EXT_CAP_ID_PRI 0x13 #define DLB2_PCI_EXT_CAP_ID_ACS 0xD @@ -73,29 +64,6 @@ #define DLB2_PCI_ACS_UF 0x10 #define DLB2_PCI_ACS_EC 0x20 -static int -dlb2_pci_find_ext_capability(struct rte_pci_device *pdev, uint32_t id) -{ - uint32_t hdr; - size_t sz; - int pos; - - pos = DLB2_PCI_CFG_SPACE_SIZE; - sz = sizeof(hdr); - - while (pos > 0xFF) { - if (rte_pci_read_config(pdev, &hdr, sz, pos) != (int)sz) - return -1; - - if (DLB2_PCI_EXT_CAP_ID(hdr) == id) - return pos; - - pos = DLB2_PCI_EXT_CAP_NEXT(hdr); - } - - return -1; -} - static int dlb2_pci_find_capability(struct rte_pci_device *pdev, uint32_t id) { uint8_t pos; @@ -299,7 +267,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return pcie_cap_offset; } - off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL; + off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL; if (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2) dev_ctl_word = 0; @@ -328,7 +296,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) slt_word2 = 0; off = DLB2_PCI_EXT_CAP_ID_PRI; - pri_cap_offset = dlb2_pci_find_ext_capability(pdev, off); + pri_cap_offset = rte_pci_find_ext_capability(pdev, off); if (pri_cap_offset >= 0) { off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ; @@ -371,7 +339,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return -1; } - off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL; + off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL; ret = rte_pci_read_config(pdev, &devctl_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to read the pcie device control\n", @@ -393,7 +361,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) /* Restore PCI config state */ if (pcie_cap_offset >= 0) { - off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL; + off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL; ret = rte_pci_write_config(pdev, &dev_ctl_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie device control at offset %d\n", @@ -470,8 +438,8 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } - off = DLB2_PCI_EXT_CAP_ID_ERR; - err_cap_offset = dlb2_pci_find_ext_capability(pdev, off); + off = RTE_PCI_EXT_CAP_ID_ERR; + err_cap_offset = rte_pci_find_ext_capability(pdev, off); if (err_cap_offset >= 0) { uint32_t tmp; @@ -556,7 +524,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } off = DLB2_PCI_EXT_CAP_ID_ACS; - acs_cap_offset = dlb2_pci_find_ext_capability(pdev, off); + acs_cap_offset = rte_pci_find_ext_capability(pdev, off); if (acs_cap_offset >= 0) { uint16_t acs_cap, acs_ctrl, acs_mask; -- 2.6.4