From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1DA55A09E9; Tue, 15 Dec 2020 08:49:57 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 606D9C9BA; Tue, 15 Dec 2020 08:49:55 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id EE11DC9B8 for ; Tue, 15 Dec 2020 08:49:53 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from jiaweiw@nvidia.com) with SMTP; 15 Dec 2020 09:49:52 +0200 Received: from nvidia.com (gen-l-vrt-281.mtl.labs.mlnx [10.237.44.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BF7nqhO023341; Tue, 15 Dec 2020 09:49:52 +0200 From: Jiawei Wang To: viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com Cc: dev@dpdk.org, rasland@nvidia.com Date: Tue, 15 Dec 2020 09:49:48 +0200 Message-Id: <1608018591-97942-2-git-send-email-jiaweiw@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1608018591-97942-1-git-send-email-jiaweiw@nvidia.com> References: <1608018591-97942-1-git-send-email-jiaweiw@nvidia.com> Subject: [dpdk-dev] [RFC 1/4] common/mlx5: query register c preserve capability via DevX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update function mlx5_devx_cmd_query_hca_attr() to add the reg_c_preserve bit query. The stored metadata in register C may be lost in NIC Tx and FDB egress while doing one one of the following operations: - packet encapsulation. - packet mirroring (multiple processing paths). - packet sampling (using Flow Sampler). If the reg_c_preserve bit is set to 1, then the above limitation is obsolete, the all metadata registers Cx preserve their values even through the operations mentioned above. Signed-off-by: Jiawei Wang --- drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 4 +++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 9c1d188..084368a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -720,6 +720,8 @@ struct mlx5_devx_obj * attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); + attr->reg_c_preserve = + MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 726e9f5..177320e 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -113,6 +113,7 @@ struct mlx5_hca_attr { uint32_t scatter_fcs_w_decap_disable:1; uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ uint32_t regex:1; + uint32_t reg_c_preserve:1; uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; struct mlx5_hca_qos_attr qos; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 58d1804..c62c3a6 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1113,7 +1113,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 regexp[0x1]; u8 reserved_at_a1[0x3]; u8 regexp_num_of_engines[0x4]; - u8 reserved_at_a8[0x3]; + u8 reserved_at_a8[0x1]; + u8 reg_c_preserve[0x1]; + u8 reserved_at_aa[0x1]; u8 log_max_srq[0x5]; u8 reserved_at_b0[0x3]; u8 regexp_log_crspace_size[0x5]; -- 1.8.3.1