From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D60ADA09E4; Fri, 29 Jan 2021 04:18:56 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BDA944067B; Fri, 29 Jan 2021 04:18:56 +0100 (CET) Received: from out0-148.mail.aliyun.com (out0-148.mail.aliyun.com [140.205.0.148]) by mails.dpdk.org (Postfix) with ESMTP id A15F240395 for ; Fri, 29 Jan 2021 04:18:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alibaba-inc.com; s=default; t=1611890332; h=From:To:Subject:Date:Message-Id; bh=7uD6uDPfNaVE3bnqxSjOSl4Ufn1MoQ0zxqT2Yw2BHDg=; b=aw9Peb6KTVhafblBDZPr+SeuL47oTjAHAkI0xAOsWB8SgG9/8dN/xTzGhqBUybWQTDz1+PrLPPmFDkH66TASTvOMPLKJFpxgMPw+wVNXJlcejxA8IInLDg4uNL10WmhLddT89MJFkLPwYgl2MG48cT6573QBvsy9Mf3zXea7FFw= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R111e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018047192; MF=huawei.xhw@alibaba-inc.com; NM=1; PH=DS; RN=10; SR=0; TI=SMTPD_---.JRv0iAd_1611890328; Received: from rs3a10040.et2sqa.z1.et2sqa.tbsite.net(mailfrom:huawei.xhw@alibaba-inc.com fp:SMTPD_---.JRv0iAd_1611890328) by smtp.aliyun-inc.com(127.0.0.1); Fri, 29 Jan 2021 11:18:51 +0800 From: "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" To: ferruh.yigit@intel.com, maxime.coquelin@redhat.com Cc: , , , , , , "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" Date: Fri, 29 Jan 2021 11:18:27 +0800 Message-Id: <1611890309-99135-1-git-send-email-huawei.xhw@alibaba-inc.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH v6 0/2] support both PIO and MMIO BAR for legacy device in virtio PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "huawei.xhw" virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong. As we need to create lots of devices, as PIO resource on x86 is very limited, we expose MMIO(memory IO) BAR. Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all other pci devices. This patchset handles different type of BAR in the similar way. In previous implementation, under igb_uio driver we get PIO address from igb_uio sysfs entry; with uio_pci_generic, we get PIO address from /proc/ioports for x86, and for other ARCHs, we get PIO address from standard PCI sysfs entry. For PIO/MMIO RW, there is different path for different drivers and arch. All of the above is too much twisted. This patchset unifies the way to get both PIO and MMIO address for different driver and ARCHs, all from standard resource attr under pci sysfs. This is most generic. We distinguish PIO and MMIO by their address like how kernel does. It is ugly but works. v2 changes: - add more explanation in the commit message v3 changes: - fix patch format issues v4 changes: - fixes for RTE_KDRV_UIO_GENERIC -> RTE_PCI_KDRV_UIO_GENERIC v5 changes: - split into three seperate patches v6 changes: - change to DEBUG level for IO bar detection in pci_uio_ioport_map - rework the code in iobar branch - fixes commit message format issue - temporarily remove the 3rd patch for vfio path, leave it for future discusssion - rework against virtio_pmd_rework_v2 huawei.xhw (2): bus/pci: use PCI standard sysfs entry to get PIO address bus/pci: support MMIO in PCI ioport accessors drivers/bus/pci/linux/pci.c | 81 ------------------- drivers/bus/pci/linux/pci_uio.c | 170 ++++++++++++++++++++++++++++------------ 2 files changed, 118 insertions(+), 133 deletions(-) -- 1.8.3.1