From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7B23A0524; Thu, 4 Feb 2021 10:06:08 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87A7D2405EC; Thu, 4 Feb 2021 10:06:08 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 59DBA2405DD for ; Thu, 4 Feb 2021 10:06:07 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from matan@nvidia.com) with SMTP; 4 Feb 2021 11:06:05 +0200 Received: from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx [10.210.16.10]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 114965jq024032; Thu, 4 Feb 2021 11:06:05 +0200 From: Matan Azrad To: dev@dpdk.org Cc: akhil.goyal@nxp.com Date: Thu, 4 Feb 2021 09:06:01 +0000 Message-Id: <1612429561-381938-1-git-send-email-matan@nvidia.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH] compress/mlx5: fix assert compilation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When ASSERT is enabled for compilation, the 2 usages of assert mechanism in the driver are failed due to typos. Fix the typos. Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions") Fixes: 37862dafcbed ("compress/mlx5: support 32-bit systems") Reported-by: Viacheslav Ovsiienko Signed-off-by: Matan Azrad Tested-by: Viacheslav Ovsiienko --- drivers/compress/mlx5/mlx5_compress.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index b47821a..46255ab 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -614,7 +614,7 @@ struct mlx5_compress_qp { op->consumed = op->src.length; op->produced = rte_be_to_cpu_32(cqe->byte_cnt); MLX5_ASSERT(cqe->byte_cnt == - qp->opaque_buf[idx].scattered_length); + opaq[idx].scattered_length); switch (xform->csum_type) { case RTE_COMP_CHECKSUM_CRC32: op->output_chksum = (uint64_t)rte_be_to_cpu_32 @@ -731,7 +731,7 @@ struct mlx5_compress_qp { return -1; } priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); - MLX5_ASSERT(qp->uar_addr); + MLX5_ASSERT(priv->uar_addr); #ifndef RTE_ARCH_64 rte_spinlock_init(&priv->uar32_sl); #endif /* RTE_ARCH_64 */ -- 1.8.3.1