From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AA4D7A034F; Wed, 31 Mar 2021 12:02:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0714B140EA6; Wed, 31 Mar 2021 12:01:36 +0200 (CEST) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id D13DA140E4A for ; Wed, 31 Mar 2021 12:01:26 +0200 (CEST) Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F9MGt2ngFz9v4t for ; Wed, 31 Mar 2021 17:59:18 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.498.0; Wed, 31 Mar 2021 18:01:18 +0800 From: "Min Hu (Connor)" To: CC: Date: Wed, 31 Mar 2021 18:01:37 +0800 Message-ID: <1617184904-55349-4-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617184904-55349-1-git-send-email-humin29@huawei.com> References: <1617184904-55349-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 03/10] net/hns3: fix the FLR miss detection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng When FLR occurs, the head pointer register of the command queue will be cleared, resulting in abnormal detection of the head pointer register of the command queue. At present, FLR is detected in this way, and the reset recovery process is executed. However, when FLR occurs, the header pointer register of the command queue is not necessarily abnormal. For example, when the driver runs normally, the value of the header pointer register of the command queue may also be 0, which will lead to the miss detection of FLR. Therefore, the judgment that whether the base address register of command queue is 0 is added to ensure that FLR not miss detection. Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Hongbo Zheng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_cmd.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 03f8048..f0c4a7f 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -195,12 +195,14 @@ hns3_cmd_csq_clean(struct hns3_hw *hw) { struct hns3_cmq_ring *csq = &hw->cmq.csq; uint32_t head; + uint32_t addr; int clean; head = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG); - if (!is_valid_csq_clean_head(csq, head)) { - hns3_err(hw, "wrong cmd head (%u, %u-%u)", head, - csq->next_to_use, csq->next_to_clean); + addr = hns3_read_dev(hw, HNS3_CMDQ_TX_ADDR_L_REG); + if (!is_valid_csq_clean_head(csq, head) || addr == 0) { + hns3_err(hw, "wrong cmd addr(%0x) head (%u, %u-%u)", addr, head, + csq->next_to_use, csq->next_to_clean); if (rte_eal_process_type() == RTE_PROC_PRIMARY) { __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); -- 2.7.4