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From: =?UTF-8?q?Juraj=20Linke=C5=A1?= <juraj.linkes@pantheon.tech>
To: bruce.richardson@intel.com, Ruifeng.Wang@arm.com,
Honnappa.Nagarahalli@arm.com, Phil.Yang@arm.com, vcchunga@amazon.com,
Dharmik.Thakkar@arm.com, jerinjacobk@gmail.com, hemant.agrawal@nxp.com,
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Date: Wed, 14 Apr 2021 14:58:38 +0200
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Subject: [dpdk-dev] [PATCH v20 3/3] config: fix Arm implementer and its SoCs
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Fix the implementer and part number of DPAA and ARMADA SoCs.
The current values of 16 cores and 1 NUMA node don't cover all SoCs from
the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
Increase these to 64 and 4 to widen the coverage.
Also increase the neoverse-n1 MAX_LCORE and MAX_NUMA_NODES to reflect
new available hardware (Amplere Altra).
Add configuration to SoC options where smaller values are needed.
Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms")
Cc: hemant.agrawal@nxp.com
Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a")
Cc: lironh@marvell.com
Fixes: d97108a33231 ("config: change defaults of armv8")
Cc: yskoh@mellanox.com
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
config/arm/meson.build | 60 +++++++++++++++++++-----------------------
1 file changed, 27 insertions(+), 33 deletions(-)
diff --git a/config/arm/meson.build b/config/arm/meson.build
index c484fe26c0..1b7c4c1cc6 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -57,7 +57,8 @@ part_number_config_arm = {
['RTE_MACHINE', '"neoverse-n1"'],
['RTE_ARM_FEATURE_ATOMICS', true],
['RTE_MAX_MEM_MB', 1048576],
- ['RTE_MAX_LCORE', 80]
+ ['RTE_MAX_LCORE', 160],
+ ['RTE_MAX_NUMA_NODES', 2]
]
},
'0xd49': {
@@ -65,7 +66,8 @@ part_number_config_arm = {
'flags': [
['RTE_MACHINE', '"neoverse-n2"'],
['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_MAX_LCORE', 64]
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 1]
]
}
}
@@ -75,8 +77,8 @@ implementer_arm = {
['RTE_MACHINE', '"armv8a"'],
['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_LCORE', 16],
- ['RTE_MAX_NUMA_NODES', 1]
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 4]
],
'part_number_config': part_number_config_arm
}
@@ -158,39 +160,13 @@ implementer_qualcomm = {
}
}
-implementer_marvell = {
- 'description': 'Marvell ARMADA',
- 'flags': [
- ['RTE_MACHINE', '"armv8a"'],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_LCORE', 16],
- ['RTE_MAX_NUMA_NODES', 1]
- ],
- 'part_number_config': part_number_config_arm
-}
-
-implementer_dpaa = {
- 'description': 'NXP DPAA',
- 'flags': [
- ['RTE_MACHINE', '"dpaa"'],
- ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
- ['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_LCORE', 16],
- ['RTE_MAX_NUMA_NODES', 1]
- ],
- 'part_number_config': part_number_config_arm
-}
-
## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
implementers = {
'generic': implementer_generic,
'0x41': implementer_arm,
'0x43': implementer_cavium,
'0x50': implementer_ampere,
- '0x51': implementer_qualcomm,
- '0x56': implementer_marvell,
- 'dpaa': implementer_dpaa
+ '0x51': implementer_qualcomm
}
# soc specific aarch64 flags have the highest priority
@@ -203,8 +179,12 @@ soc_generic = {
soc_armada = {
'description': 'Marvell ARMADA',
- 'implementer': '0x56',
+ 'implementer': '0x41',
'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'numa': false
}
@@ -212,13 +192,23 @@ soc_bluefield = {
'description': 'NVIDIA BlueField',
'implementer': '0x41',
'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'numa': false
}
soc_dpaa = {
'description': 'NXP DPAA',
- 'implementer': 'dpaa',
+ 'implementer': '0x41',
'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'numa': false
}
@@ -262,6 +252,10 @@ soc_octeontx2 = {
soc_stingray = {
'description': 'Broadcom Stingray',
'implementer': '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'part_number': '0xd08',
'numa': false
}
--
2.20.1