From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2DEDFA0562; Wed, 14 Apr 2021 14:59:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA7D1161AAA; Wed, 14 Apr 2021 14:58:51 +0200 (CEST) Received: from lb.pantheon.sk (lb.pantheon.sk [46.229.239.20]) by mails.dpdk.org (Postfix) with ESMTP id CCA03161A95 for ; Wed, 14 Apr 2021 14:58:46 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by lb.pantheon.sk (Postfix) with ESMTP id 04D62C566D; Wed, 14 Apr 2021 14:58:44 +0200 (CEST) X-Virus-Scanned: amavisd-new at siecit.sk Received: from lb.pantheon.sk ([127.0.0.1]) by localhost (lb.pantheon.sk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4Tsf1ITSKCh1; Wed, 14 Apr 2021 14:58:44 +0200 (CEST) Received: from service-node1.lab.pantheon.local (unknown [46.229.239.141]) by lb.pantheon.sk (Postfix) with ESMTP id 96E28C5671; Wed, 14 Apr 2021 14:58:41 +0200 (CEST) From: =?UTF-8?q?Juraj=20Linke=C5=A1?= To: bruce.richardson@intel.com, Ruifeng.Wang@arm.com, Honnappa.Nagarahalli@arm.com, Phil.Yang@arm.com, vcchunga@amazon.com, Dharmik.Thakkar@arm.com, jerinjacobk@gmail.com, hemant.agrawal@nxp.com, ajit.khaparde@broadcom.com, ferruh.yigit@intel.com, aboyer@pensando.io Cc: dev@dpdk.org, =?UTF-8?q?Juraj=20Linke=C5=A1?= , lironh@marvell.com, yskoh@mellanox.com Date: Wed, 14 Apr 2021 14:58:38 +0200 Message-Id: <1618405118-20187-4-git-send-email-juraj.linkes@pantheon.tech> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618405118-20187-1-git-send-email-juraj.linkes@pantheon.tech> References: <1617957679-7751-1-git-send-email-juraj.linkes@pantheon.tech> <1618405118-20187-1-git-send-email-juraj.linkes@pantheon.tech> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v20 3/3] config: fix Arm implementer and its SoCs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix the implementer and part number of DPAA and ARMADA SoCs. The current values of 16 cores and 1 NUMA node don't cover all SoCs from the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes. Increase these to 64 and 4 to widen the coverage. Also increase the neoverse-n1 MAX_LCORE and MAX_NUMA_NODES to reflect new available hardware (Amplere Altra). Add configuration to SoC options where smaller values are needed. Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms") Cc: hemant.agrawal@nxp.com Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a") Cc: lironh@marvell.com Fixes: d97108a33231 ("config: change defaults of armv8") Cc: yskoh@mellanox.com Signed-off-by: Juraj Linkeš Reviewed-by: Honnappa Nagarahalli Reviewed-by: Liron Himi Acked-by: Pavan Nikhilesh Acked-by: Viacheslav Ovsiienko --- config/arm/meson.build | 60 +++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index c484fe26c0..1b7c4c1cc6 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -57,7 +57,8 @@ part_number_config_arm = { ['RTE_MACHINE', '"neoverse-n1"'], ['RTE_ARM_FEATURE_ATOMICS', true], ['RTE_MAX_MEM_MB', 1048576], - ['RTE_MAX_LCORE', 80] + ['RTE_MAX_LCORE', 160], + ['RTE_MAX_NUMA_NODES', 2] ] }, '0xd49': { @@ -65,7 +66,8 @@ part_number_config_arm = { 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], ['RTE_ARM_FEATURE_ATOMICS', true], - ['RTE_MAX_LCORE', 64] + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 1] ] } } @@ -75,8 +77,8 @@ implementer_arm = { ['RTE_MACHINE', '"armv8a"'], ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_LCORE', 16], - ['RTE_MAX_NUMA_NODES', 1] + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 4] ], 'part_number_config': part_number_config_arm } @@ -158,39 +160,13 @@ implementer_qualcomm = { } } -implementer_marvell = { - 'description': 'Marvell ARMADA', - 'flags': [ - ['RTE_MACHINE', '"armv8a"'], - ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_LCORE', 16], - ['RTE_MAX_NUMA_NODES', 1] - ], - 'part_number_config': part_number_config_arm -} - -implementer_dpaa = { - 'description': 'NXP DPAA', - 'flags': [ - ['RTE_MACHINE', '"dpaa"'], - ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false], - ['RTE_USE_C11_MEM_MODEL', true], - ['RTE_CACHE_LINE_SIZE', 64], - ['RTE_MAX_LCORE', 16], - ['RTE_MAX_NUMA_NODES', 1] - ], - 'part_number_config': part_number_config_arm -} - ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual) implementers = { 'generic': implementer_generic, '0x41': implementer_arm, '0x43': implementer_cavium, '0x50': implementer_ampere, - '0x51': implementer_qualcomm, - '0x56': implementer_marvell, - 'dpaa': implementer_dpaa + '0x51': implementer_qualcomm } # soc specific aarch64 flags have the highest priority @@ -203,8 +179,12 @@ soc_generic = { soc_armada = { 'description': 'Marvell ARMADA', - 'implementer': '0x56', + 'implementer': '0x41', 'part_number': '0xd08', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'numa': false } @@ -212,13 +192,23 @@ soc_bluefield = { 'description': 'NVIDIA BlueField', 'implementer': '0x41', 'part_number': '0xd08', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'numa': false } soc_dpaa = { 'description': 'NXP DPAA', - 'implementer': 'dpaa', + 'implementer': '0x41', 'part_number': '0xd08', + 'flags': [ + ['RTE_MACHINE', '"dpaa"'], + ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false], + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'numa': false } @@ -262,6 +252,10 @@ soc_octeontx2 = { soc_stingray = { 'description': 'Broadcom Stingray', 'implementer': '0x41', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], 'part_number': '0xd08', 'numa': false } -- 2.20.1