* [dpdk-dev] [PATCH 1/3] net/hns3: support runtime config of mask device capability
2021-04-15 3:51 [dpdk-dev] [PATCH 0/3] some features about hns3 PMD Min Hu (Connor)
@ 2021-04-15 3:52 ` Min Hu (Connor)
2021-04-15 3:52 ` [dpdk-dev] [PATCH 2/3] net/hns3: support Rx checksum simple process Min Hu (Connor)
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Min Hu (Connor) @ 2021-04-15 3:52 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Chengwen Feng <fengchengwen@huawei.com>
This patch supports runtime config of mask device capability, it was
used to mask the capability which queried from firmware.
The device args key is "dev_caps_mask" which takes hexadecimal bitmask
where each bit represents whether mask corresponding capability.
Its main purpose is to debug and avoid problems.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
---
doc/guides/nics/hns3.rst | 9 ++++++
drivers/net/hns3/hns3_cmd.c | 67 +++++++++++++++++++++++++++++++++++++++
drivers/net/hns3/hns3_ethdev.c | 24 +++++++++++++-
drivers/net/hns3/hns3_ethdev.h | 4 +++
drivers/net/hns3/hns3_ethdev_vf.c | 3 +-
5 files changed, 105 insertions(+), 2 deletions(-)
diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst
index 3366562..9592551 100644
--- a/doc/guides/nics/hns3.rst
+++ b/doc/guides/nics/hns3.rst
@@ -84,6 +84,15 @@ Runtime Config Options
be first checked, if meets, use the ``vec``. Then, ``simple``, at last
``common``.
+- ``dev_caps_mask`` (default ``0``)
+
+ Used to mask the capability which queried from firmware.
+ This args take hexadecimal bitmask where each bit represents whether mask
+ corresponding capability. eg. If the capability is 0xFFFF queried from
+ firmware, and the args value is 0xF which means the bit0~bit3 should be
+ masked off, then the capability will be 0xFFF0.
+ Its main purpose is to debug and avoid problems.
+
Driver compilation and testing
------------------------------
diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index 75d5299..04e5786 100644
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -411,6 +411,68 @@ hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)
return retval;
}
+static const char *
+hns3_get_caps_name(uint32_t caps_id)
+{
+ const struct {
+ enum HNS3_CAPS_BITS caps;
+ const char *name;
+ } dev_caps[] = {
+ { HNS3_CAPS_UDP_GSO_B, "udp_gso" },
+ { HNS3_CAPS_ATR_B, "atr" },
+ { HNS3_CAPS_FD_QUEUE_REGION_B, "fd_queue_region" },
+ { HNS3_CAPS_PTP_B, "ptp" },
+ { HNS3_CAPS_INT_QL_B, "int_ql" },
+ { HNS3_CAPS_SIMPLE_BD_B, "simple_bd" },
+ { HNS3_CAPS_TX_PUSH_B, "tx_push" },
+ { HNS3_CAPS_PHY_IMP_B, "phy_imp" },
+ { HNS3_CAPS_TQP_TXRX_INDEP_B, "tqp_txrx_indep" },
+ { HNS3_CAPS_HW_PAD_B, "hw_pad" },
+ { HNS3_CAPS_STASH_B, "stash" },
+ { HNS3_CAPS_UDP_TUNNEL_CSUM_B, "udp_tunnel_csum" },
+ { HNS3_CAPS_RAS_IMP_B, "ras_imp" },
+ { HNS3_CAPS_FEC_B, "fec" },
+ { HNS3_CAPS_PAUSE_B, "pause" },
+ { HNS3_CAPS_RXD_ADV_LAYOUT_B, "rxd_adv_layout" }
+ };
+ uint32_t i;
+
+ for (i = 0; i < RTE_DIM(dev_caps); i++) {
+ if (dev_caps[i].caps == caps_id)
+ return dev_caps[i].name;
+ }
+
+ return "unknown";
+}
+
+static void
+hns3_mask_capability(struct hns3_hw *hw,
+ struct hns3_query_version_cmd *cmd)
+{
+#define MAX_CAPS_BIT 64
+
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ uint64_t caps_org, caps_new, caps_masked;
+ uint32_t i;
+
+ if (hns->dev_caps_mask == 0)
+ return;
+
+ memcpy(&caps_org, &cmd->caps[0], sizeof(caps_org));
+ caps_org = rte_le_to_cpu_64(caps_org);
+ caps_new = caps_org ^ (caps_org & hns->dev_caps_mask);
+ caps_masked = caps_org ^ caps_new;
+ caps_new = rte_cpu_to_le_64(caps_new);
+ memcpy(&cmd->caps[0], &caps_new, sizeof(caps_new));
+
+ for (i = 0; i < MAX_CAPS_BIT; i++) {
+ if (!(caps_masked & BIT_ULL(i)))
+ continue;
+ hns3_info(hw, "mask capabiliy: id-%u, name-%s.",
+ i, hns3_get_caps_name(i));
+ }
+}
+
static void
hns3_parse_capability(struct hns3_hw *hw,
struct hns3_query_version_cmd *cmd)
@@ -478,6 +540,11 @@ hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
return ret;
hw->fw_version = rte_le_to_cpu_32(resp->firmware);
+ /*
+ * Make sure mask the capability before parse capability because it
+ * may overwrite resp's data.
+ */
+ hns3_mask_capability(hw, resp);
hns3_parse_capability(hw, resp);
return 0;
diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index 1832d26..8601cf0 100644
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -7208,6 +7208,19 @@ hns3_get_io_hint_func_name(uint32_t hint)
}
}
+static int
+hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
+{
+ uint64_t val;
+
+ RTE_SET_USED(key);
+
+ val = strtoull(value, NULL, 16);
+ *(uint64_t *)extra_args = val;
+
+ return 0;
+}
+
void
hns3_parse_devargs(struct rte_eth_dev *dev)
{
@@ -7215,6 +7228,7 @@ hns3_parse_devargs(struct rte_eth_dev *dev)
uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
struct hns3_hw *hw = &hns->hw;
+ uint64_t dev_caps_mask = 0;
struct rte_kvargs *kvlist;
if (dev->device->devargs == NULL)
@@ -7228,6 +7242,8 @@ hns3_parse_devargs(struct rte_eth_dev *dev)
&hns3_parse_io_hint_func, &rx_func_hint);
rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
&hns3_parse_io_hint_func, &tx_func_hint);
+ rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
+ &hns3_parse_dev_caps_mask, &dev_caps_mask);
rte_kvargs_free(kvlist);
if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
@@ -7238,6 +7254,11 @@ hns3_parse_devargs(struct rte_eth_dev *dev)
hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
hns3_get_io_hint_func_name(tx_func_hint));
hns->tx_func_hint = tx_func_hint;
+
+ if (dev_caps_mask != 0)
+ hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
+ HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
+ hns->dev_caps_mask = dev_caps_mask;
}
static const struct eth_dev_ops hns3_eth_dev_ops = {
@@ -7505,6 +7526,7 @@ RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
- HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
+ HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
+ HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);
diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index 7b7d359..07b313c 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -822,6 +822,8 @@ struct hns3_adapter {
uint32_t rx_func_hint;
uint32_t tx_func_hint;
+ uint64_t dev_caps_mask;
+
struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
};
@@ -836,6 +838,8 @@ enum {
#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
+#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
+
#define HNS3_DEV_SUPPORT_DCB_B 0x0
#define HNS3_DEV_SUPPORT_COPPER_B 0x1
#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c
index 5770c47..273a938 100644
--- a/drivers/net/hns3/hns3_ethdev_vf.c
+++ b/drivers/net/hns3/hns3_ethdev_vf.c
@@ -3074,4 +3074,5 @@ RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
- HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
+ HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
+ HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread* [dpdk-dev] [PATCH 2/3] net/hns3: support Rx checksum simple process
2021-04-15 3:51 [dpdk-dev] [PATCH 0/3] some features about hns3 PMD Min Hu (Connor)
2021-04-15 3:52 ` [dpdk-dev] [PATCH 1/3] net/hns3: support runtime config of mask device capability Min Hu (Connor)
@ 2021-04-15 3:52 ` Min Hu (Connor)
2021-04-15 3:52 ` [dpdk-dev] [PATCH 3/3] net/hns3: check max SIMD bitwidth Min Hu (Connor)
2021-04-19 17:16 ` [dpdk-dev] [PATCH 0/3] some features about hns3 PMD Ferruh Yigit
3 siblings, 0 replies; 5+ messages in thread
From: Min Hu (Connor) @ 2021-04-15 3:52 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Chengwen Feng <fengchengwen@huawei.com>
Currently, the L3L4P/L3E/L4E/OL3E/OL4E fields in Rx descriptor used to
indicate hardware checksum result:
1. L3L4P: indicates hardware has processed L3L4 checksum for this
packet, if this bit is 1 then L3E/L4E/OL3E/OL4E is trustable.
2. L3E: L3 checksum error indication, 1 means with error.
3. L4E: L4 checksum error indication, 1 means with error.
4. OL3E: outer L3 checksum error indication, 1 means with error.
5. OL4E: outer L4 checksum error indication, 1 means with error.
Driver will set the good checksum flag through packet type and
L3E/L4E/OL3E/OL4E when L3L4P is 1, it runs as follows:
1. If packet type indicates it's tunnel packet:
1.1. If packet type indicates it has inner L3 and L3E is zero, then
mark the IP checksum good.
1.2. If packet type indicates it has inner L4 and L4E is zero, then
mark the L4 checksum good.
1.3. If packet type indicates it has outer L4 and OL4E is zero, then
mark the outer L4 checksum good.
2. If packet type indicates it's not tunnel packet:
2.1. If packet type indicates it has L3 and L3E is zero, then mark the
IP checksum good.
2.2. If packet type indicates it has L4 and L4E is zero, then mark the
L4 checksum good.
As described above, the good checksum calculation is time consuming,
it impacts the Rx performance.
By balancing performance and functionality, driver uses the following
scheme to set good checksum flag when L3L4P is 1:
1. If L3E is zero, then mark the IP checksum good.
2. If L4E is zero, then mark the L4 checksum good.
The performance gains are 3% in small packet iofwd scenarios.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
---
drivers/net/hns3/hns3_rxtx.c | 14 +----
drivers/net/hns3/hns3_rxtx.h | 103 ++++++++++++++--------------------
drivers/net/hns3/hns3_rxtx_vec_neon.h | 7 +--
drivers/net/hns3/hns3_rxtx_vec_sve.c | 6 +-
4 files changed, 45 insertions(+), 85 deletions(-)
diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
index bec7fae..c29c0cf 100644
--- a/drivers/net/hns3/hns3_rxtx.c
+++ b/drivers/net/hns3/hns3_rxtx.c
@@ -2400,7 +2400,6 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
struct rte_mbuf *nmb; /* pointer of the new mbuf */
struct rte_mbuf *rxm;
uint32_t bd_base_info;
- uint32_t cksum_err;
uint32_t l234_info;
uint32_t ol_info;
uint64_t dma_addr;
@@ -2475,8 +2474,7 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
/* Load remained descriptor data and extract necessary fields */
l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
- ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info,
- l234_info, &cksum_err);
+ ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info, l234_info);
if (unlikely(ret))
goto pkt_err;
@@ -2485,9 +2483,6 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
rxm->ol_flags |= PKT_RX_IEEE1588_PTP;
- if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
- hns3_rx_set_cksum_flag(rxm, rxm->packet_type,
- cksum_err);
hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
/* Increment bytes counter */
@@ -2526,7 +2521,6 @@ hns3_recv_scattered_pkts(void *rx_queue,
struct rte_mbuf *rxm;
struct rte_eth_dev *dev;
uint32_t bd_base_info;
- uint32_t cksum_err;
uint32_t l234_info;
uint32_t gro_size;
uint32_t ol_info;
@@ -2700,17 +2694,13 @@ hns3_recv_scattered_pkts(void *rx_queue,
l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
- l234_info, &cksum_err);
+ l234_info);
if (unlikely(ret))
goto pkt_err;
first_seg->packet_type = hns3_rx_calc_ptype(rxq,
l234_info, ol_info);
- if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
- hns3_rx_set_cksum_flag(first_seg,
- first_seg->packet_type,
- cksum_err);
hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
/* Increment bytes counter */
diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h
index 10a6c64..9dfae61 100644
--- a/drivers/net/hns3/hns3_rxtx.h
+++ b/drivers/net/hns3/hns3_rxtx.h
@@ -541,19 +541,50 @@ enum hns3_cksum_status {
extern uint64_t hns3_timestamp_rx_dynflag;
extern int hns3_timestamp_dynfield_offset;
-static inline int
-hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
- uint32_t bd_base_info, uint32_t l234_info,
- uint32_t *cksum_err)
+static inline void
+hns3_rx_set_cksum_flag(struct hns3_rx_queue *rxq,
+ struct rte_mbuf *rxm,
+ uint32_t l234_info)
{
-#define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
- BIT(HNS3_RXD_TRUNCATE_B))
-#define CHECKSUM_ERR_FLAG (BIT(HNS3_RXD_L3E_B) | \
+#define HNS3_RXD_CKSUM_ERR_MASK (BIT(HNS3_RXD_L3E_B) | \
BIT(HNS3_RXD_L4E_B) | \
BIT(HNS3_RXD_OL3E_B) | \
BIT(HNS3_RXD_OL4E_B))
- uint32_t tmp = 0;
+ if (likely((l234_info & HNS3_RXD_CKSUM_ERR_MASK) == 0)) {
+ rxm->ol_flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
+ return;
+ }
+
+ if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
+ rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
+ rxq->dfx_stats.l3_csum_errors++;
+ } else {
+ rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+ }
+
+ if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
+ rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ rxq->dfx_stats.l4_csum_errors++;
+ } else {
+ rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
+ }
+
+ if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B)))
+ rxq->dfx_stats.ol3_csum_errors++;
+
+ if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
+ rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
+ rxq->dfx_stats.ol4_csum_errors++;
+ }
+}
+
+static inline int
+hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
+ uint32_t bd_base_info, uint32_t l234_info)
+{
+#define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
+ BIT(HNS3_RXD_TRUNCATE_B))
/*
* If packet len bigger than mtu when recv with no-scattered algorithm,
@@ -572,64 +603,12 @@ hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
return -EINVAL;
}
- if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
- if (likely((l234_info & CHECKSUM_ERR_FLAG) == 0)) {
- *cksum_err = 0;
- return 0;
- }
-
- if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
- rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
- rxq->dfx_stats.l3_csum_errors++;
- tmp |= HNS3_L3_CKSUM_ERR;
- }
-
- if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
- rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
- rxq->dfx_stats.l4_csum_errors++;
- tmp |= HNS3_L4_CKSUM_ERR;
- }
-
- if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
- rxq->dfx_stats.ol3_csum_errors++;
- tmp |= HNS3_OUTER_L3_CKSUM_ERR;
- }
-
- if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
- rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
- rxq->dfx_stats.ol4_csum_errors++;
- tmp |= HNS3_OUTER_L4_CKSUM_ERR;
- }
- }
- *cksum_err = tmp;
+ if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
+ hns3_rx_set_cksum_flag(rxq, rxm, l234_info);
return 0;
}
-static inline void
-hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, const uint64_t packet_type,
- const uint32_t cksum_err)
-{
- if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
- if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
- (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
- rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
- if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
- (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
- rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
- if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
- (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
- rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
- } else {
- if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
- (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
- rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
- if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
- (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
- rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
- }
-}
-
static inline uint32_t
hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,
const uint32_t ol_info)
diff --git a/drivers/net/hns3/hns3_rxtx_vec_neon.h b/drivers/net/hns3/hns3_rxtx_vec_neon.h
index 14d6fb0..a58bc3a 100644
--- a/drivers/net/hns3/hns3_rxtx_vec_neon.h
+++ b/drivers/net/hns3/hns3_rxtx_vec_neon.h
@@ -98,7 +98,6 @@ hns3_desc_parse_field(struct hns3_rx_queue *rxq,
uint32_t l234_info, ol_info, bd_base_info;
struct rte_mbuf *pkt;
uint32_t retcode = 0;
- uint32_t cksum_err;
uint32_t i;
int ret;
@@ -111,17 +110,13 @@ hns3_desc_parse_field(struct hns3_rx_queue *rxq,
l234_info = rxdp[i].rx.l234_info;
ol_info = rxdp[i].rx.ol_info;
bd_base_info = rxdp[i].rx.bd_base_info;
- ret = hns3_handle_bdinfo(rxq, pkt, bd_base_info,
- l234_info, &cksum_err);
+ ret = hns3_handle_bdinfo(rxq, pkt, bd_base_info, l234_info);
if (unlikely(ret)) {
retcode |= 1u << i;
continue;
}
pkt->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
- if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
- hns3_rx_set_cksum_flag(pkt, pkt->packet_type,
- cksum_err);
/* Increment bytes counter */
rxq->basic_stats.bytes += pkt->pkt_len;
diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c
index 2eaf692..f45aaad 100644
--- a/drivers/net/hns3/hns3_rxtx_vec_sve.c
+++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c
@@ -39,7 +39,6 @@ hns3_desc_parse_field_sve(struct hns3_rx_queue *rxq,
uint32_t bd_vld_num)
{
uint32_t retcode = 0;
- uint32_t cksum_err;
int ret, i;
for (i = 0; i < (int)bd_vld_num; i++) {
@@ -47,7 +46,7 @@ hns3_desc_parse_field_sve(struct hns3_rx_queue *rxq,
rx_pkts[i]->ol_flags = PKT_RX_RSS_HASH;
ret = hns3_handle_bdinfo(rxq, rx_pkts[i], key->bd_base_info[i],
- key->l234_info[i], &cksum_err);
+ key->l234_info[i]);
if (unlikely(ret)) {
retcode |= 1u << i;
continue;
@@ -55,9 +54,6 @@ hns3_desc_parse_field_sve(struct hns3_rx_queue *rxq,
rx_pkts[i]->packet_type = hns3_rx_calc_ptype(rxq,
key->l234_info[i], key->ol_info[i]);
- if (likely(key->bd_base_info[i] & BIT(HNS3_RXD_L3L4P_B)))
- hns3_rx_set_cksum_flag(rx_pkts[i],
- rx_pkts[i]->packet_type, cksum_err);
/* Increment bytes counter */
rxq->basic_stats.bytes += rx_pkts[i]->pkt_len;
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread* [dpdk-dev] [PATCH 3/3] net/hns3: check max SIMD bitwidth
2021-04-15 3:51 [dpdk-dev] [PATCH 0/3] some features about hns3 PMD Min Hu (Connor)
2021-04-15 3:52 ` [dpdk-dev] [PATCH 1/3] net/hns3: support runtime config of mask device capability Min Hu (Connor)
2021-04-15 3:52 ` [dpdk-dev] [PATCH 2/3] net/hns3: support Rx checksum simple process Min Hu (Connor)
@ 2021-04-15 3:52 ` Min Hu (Connor)
2021-04-19 17:16 ` [dpdk-dev] [PATCH 0/3] some features about hns3 PMD Ferruh Yigit
3 siblings, 0 replies; 5+ messages in thread
From: Min Hu (Connor) @ 2021-04-15 3:52 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Chengwen Feng <fengchengwen@huawei.com>
This patch supports check max SIMD bitwidth when choosing NEON and SVE
vector path.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
---
drivers/net/hns3/hns3_rxtx.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
index c29c0cf..85ee67a 100644
--- a/drivers/net/hns3/hns3_rxtx.c
+++ b/drivers/net/hns3/hns3_rxtx.c
@@ -13,6 +13,7 @@
#include <rte_malloc.h>
#if defined(RTE_ARCH_ARM64)
#include <rte_cpuflags.h>
+#include <rte_vect.h>
#endif
#include "hns3_ethdev.h"
@@ -2788,6 +2789,8 @@ static bool
hns3_get_default_vec_support(void)
{
#if defined(RTE_ARCH_ARM64)
+ if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
+ return false;
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
return true;
#endif
@@ -2798,6 +2801,8 @@ static bool
hns3_get_sve_support(void)
{
#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
+ if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
+ return false;
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
return true;
#endif
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [dpdk-dev] [PATCH 0/3] some features about hns3 PMD
2021-04-15 3:51 [dpdk-dev] [PATCH 0/3] some features about hns3 PMD Min Hu (Connor)
` (2 preceding siblings ...)
2021-04-15 3:52 ` [dpdk-dev] [PATCH 3/3] net/hns3: check max SIMD bitwidth Min Hu (Connor)
@ 2021-04-19 17:16 ` Ferruh Yigit
3 siblings, 0 replies; 5+ messages in thread
From: Ferruh Yigit @ 2021-04-19 17:16 UTC (permalink / raw)
To: Min Hu (Connor), dev
On 4/15/2021 4:51 AM, Min Hu (Connor) wrote:
> This patch set includes 3 features:
> check max SIMD bitwidth.
> support Rx checksum simple process.
> support runtime config of mask device capability.
>
> Chengwen Feng (3):
> net/hns3: support runtime config of mask device capability
> net/hns3: support Rx checksum simple process
> net/hns3: check max SIMD bitwidth
>
Series applied to dpdk-next-net/main, thanks.
^ permalink raw reply [flat|nested] 5+ messages in thread