From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 489FCA0562; Sat, 17 Apr 2021 11:54:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A3CA7161DA5; Sat, 17 Apr 2021 11:54:53 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id C1B6A406A3 for ; Sat, 17 Apr 2021 11:54:50 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FMpK90MSdz17R8S for ; Sat, 17 Apr 2021 17:52:29 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Sat, 17 Apr 2021 17:54:44 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 17 Apr 2021 17:54:53 +0800 Message-ID: <1618653299-40380-2-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618653299-40380-1-git-send-email-humin29@huawei.com> References: <1618653299-40380-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 1/7] net/hns3: check max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng This patch supports check max SIMD bitwidth when choosing NEON and SVE vector path. Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 9bb30fc..f2022a5 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -13,6 +13,7 @@ #include #if defined(RTE_ARCH_ARM64) #include +#include #endif #include "hns3_ethdev.h" @@ -2800,6 +2801,8 @@ static bool hns3_get_default_vec_support(void) { #if defined(RTE_ARCH_ARM64) + if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) + return false; if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) return true; #endif @@ -2810,6 +2813,8 @@ static bool hns3_get_sve_support(void) { #if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) + if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) + return false; if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) return true; #endif -- 2.7.4