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From: "Min Hu (Connor)" <humin29@huawei.com>
To: <dev@dpdk.org>
Cc: <ferruh.yigit@intel.com>
Subject: [dpdk-dev] [PATCH 2/7] net/hns3: Rx vector add compile-time verify
Date: Sat, 17 Apr 2021 17:54:54 +0800	[thread overview]
Message-ID: <1618653299-40380-3-git-send-email-humin29@huawei.com> (raw)
In-Reply-To: <1618653299-40380-1-git-send-email-humin29@huawei.com>

From: Chengwen Feng <fengchengwen@huawei.com>

According the Rx vector implement, it depends on the MBUF's fields
(such as rearm_data/rx_descriptor_fields1) layout, this patch adds
compile-time verifies with this.

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
---
 drivers/net/hns3/hns3_rxtx_vec.c      | 22 ++++++++++++++++++++++
 drivers/net/hns3/hns3_rxtx_vec_neon.h |  8 ++++++++
 drivers/net/hns3/hns3_rxtx_vec_sve.c  |  6 ++++++
 3 files changed, 36 insertions(+)

diff --git a/drivers/net/hns3/hns3_rxtx_vec.c b/drivers/net/hns3/hns3_rxtx_vec.c
index 08a86e0..dc1e1ae 100644
--- a/drivers/net/hns3/hns3_rxtx_vec.c
+++ b/drivers/net/hns3/hns3_rxtx_vec.c
@@ -147,6 +147,28 @@ hns3_rxq_vec_setup_rearm_data(struct hns3_rx_queue *rxq)
 	mb_def.port = rxq->port_id;
 	rte_mbuf_refcnt_set(&mb_def, 1);
 
+	/* compile-time verifies the rearm_data first 8bytes */
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) <
+			 offsetof(struct rte_mbuf, rearm_data));
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) <
+			 offsetof(struct rte_mbuf, rearm_data));
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) <
+			 offsetof(struct rte_mbuf, rearm_data));
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) <
+			 offsetof(struct rte_mbuf, rearm_data));
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) <
+			 offsetof(struct rte_mbuf, rearm_data));
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) -
+			 offsetof(struct rte_mbuf, rearm_data) > 6);
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
+			 offsetof(struct rte_mbuf, rearm_data) > 6);
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
+			 offsetof(struct rte_mbuf, rearm_data) > 6);
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
+			 offsetof(struct rte_mbuf, rearm_data) > 6);
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
+			 offsetof(struct rte_mbuf, rearm_data) > 6);
+
 	/* prevent compiler reordering: rearm_data covers previous fields */
 	rte_compiler_barrier();
 	p = (uintptr_t)&mb_def.rearm_data;
diff --git a/drivers/net/hns3/hns3_rxtx_vec_neon.h b/drivers/net/hns3/hns3_rxtx_vec_neon.h
index 14d6fb0..69af7b3 100644
--- a/drivers/net/hns3/hns3_rxtx_vec_neon.h
+++ b/drivers/net/hns3/hns3_rxtx_vec_neon.h
@@ -161,6 +161,14 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq,
 		0, 0, 0,      /* ignore non-length fields */
 	};
 
+	/* compile-time verifies the shuffle mask */
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
+			 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
+			 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash.rss) !=
+			 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
+
 	for (pos = 0; pos < nb_pkts; pos += HNS3_DEFAULT_DESCS_PER_LOOP,
 				     rxdp += HNS3_DEFAULT_DESCS_PER_LOOP) {
 		uint64x2x2_t descs[HNS3_DEFAULT_DESCS_PER_LOOP];
diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c
index 2eaf692..1fd87ca 100644
--- a/drivers/net/hns3/hns3_rxtx_vec_sve.c
+++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c
@@ -122,6 +122,12 @@ hns3_recv_burst_vec_sve(struct hns3_rx_queue *__restrict rxq,
 	svuint32_t rss_tbl1 = svld1_u32(PG32_256BIT, rss_adjust);
 	svuint32_t rss_tbl2 = svld1_u32(PG32_256BIT, &rss_adjust[8]);
 
+	/* compile-time verifies the xlen_adjust mask */
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
+			 offsetof(struct rte_mbuf, pkt_len) + 4);
+	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
+			 offsetof(struct rte_mbuf, data_len) + 2);
+
 	for (pos = 0; pos < nb_pkts; pos += HNS3_SVE_DEFAULT_DESCS_PER_LOOP,
 				     rxdp += HNS3_SVE_DEFAULT_DESCS_PER_LOOP) {
 		svuint64_t vld_clz, mbp1st, mbp2st, mbuf_init;
-- 
2.7.4


  parent reply	other threads:[~2021-04-17  9:55 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-17  9:54 [dpdk-dev] [PATCH 0/7] features and bugfix for hns3 PMD Min Hu (Connor)
2021-04-17  9:54 ` [dpdk-dev] [PATCH 1/7] net/hns3: check max SIMD bitwidth Min Hu (Connor)
2021-04-20  0:16   ` Ferruh Yigit
2021-04-17  9:54 ` Min Hu (Connor) [this message]
2021-04-17  9:54 ` [dpdk-dev] [PATCH 3/7] net/hns3: remove redundant code about mbx Min Hu (Connor)
2021-04-17  9:54 ` [dpdk-dev] [PATCH 4/7] net/hns3: fix the check for DCB mode Min Hu (Connor)
2021-04-17  9:54 ` [dpdk-dev] [PATCH 5/7] net/hns3: fix the check for VMDq mode Min Hu (Connor)
2021-04-17  9:54 ` [dpdk-dev] [PATCH 6/7] net/hns3: fix FDIR lock bug Min Hu (Connor)
2021-04-17  9:54 ` [dpdk-dev] [PATCH 7/7] net/hns3: move the link speeds check to dev configure Min Hu (Connor)
2021-04-20  0:42 ` [dpdk-dev] [PATCH 0/7] features and bugfix for hns3 PMD Ferruh Yigit

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