From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 761DAA0547; Wed, 19 May 2021 13:50:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA72340041; Wed, 19 May 2021 13:50:06 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id CD6BA4003F for ; Wed, 19 May 2021 13:50:05 +0200 (CEST) Received: from dggems703-chm.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FlWL16NrGzpdnZ; Wed, 19 May 2021 19:46:33 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggems703-chm.china.huawei.com (10.3.19.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 19 May 2021 19:50:03 +0800 Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 19 May 2021 19:50:02 +0800 From: Chengwen Feng To: , , CC: , , , , , , , , Date: Wed, 19 May 2021 19:47:01 +0800 Message-ID: <1621424821-53240-1-git-send-email-fengchengwen@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH] net/hns3: fix compile error with gcc8.3 and crossfile thunderx2 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Compile error with gcc8.3 and crossfile arm64_thunderx2_linux_gcc: ../drivers/net/hns3/hns3_rxtx_vec_sve.c cc1: error: switch ‘-mcpu=armv8.1-a’ conflicts with ‘-march=armv8.2-a’ switch [-Werror] ../drivers/net/hns3/hns3_rxtx_vec_sve.c:5:10: fatal error: arm_sve.h: No such file or directory 5 | #include The root cause is that gcc8.3 supports SVE, but it doesn't support compile ACLE[1] SVE code, and the hns3_rxtx_vec_sve.c was written by ACLE SVE code. This patch also filters out '-march=' '-mcpu' '-mtune' when compile with hns3_rxtx_vec_sve.c. [1] ACLE: Arm C Language Extensions, user should include when writting ACLE SVE code. Fixes: 203fbaf8813d ("net/hns3: refactor SVE code compile method") --- drivers/net/hns3/meson.build | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 8563d70..5f9af9b 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -39,16 +39,22 @@ if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') # compile SVE when: # a. support SVE in minimum instruction set baseline # b. it's not minimum instruction set, but compiler support - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' + if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and cc.check_header('arm_sve.h') cflags += ['-DCC_SVE_SUPPORT'] sources += files('hns3_rxtx_vec_sve.c') - elif cc.has_argument('-march=armv8.2-a+sve') - cflags += ['-DCC_SVE_SUPPORT'] + elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h') + sve_cflags = ['-DCC_SVE_SUPPORT'] + foreach flag: cflags + # filterout -march -mcpu -mtune + if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune=')) + sve_cflags += flag + endif + endforeach hns3_sve_lib = static_library('hns3_sve_lib', 'hns3_rxtx_vec_sve.c', dependencies: [static_rte_ethdev], include_directories: includes, - c_args: [cflags, '-march=armv8.2-a+sve']) + c_args: [sve_cflags, '-march=armv8.2-a+sve']) objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') endif endif -- 2.8.1