From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EAFE3A0524; Wed, 2 Jun 2021 18:46:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5E3DC4113A; Wed, 2 Jun 2021 18:45:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EE59A410FB for ; Wed, 2 Jun 2021 18:45:30 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152Gasef016164; Wed, 2 Jun 2021 09:45:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=iIltUCF2xxgJvgvUIMeQgvBneJzQLjLby6sRHiX8Q80=; b=EurW1PWr3KcG3xnfc/nk/0Mpm2JBwU+9WmX069DtZZzyB+LBIwhzJlWeh5pF0PxdIwaF 7KbyhnvAs8/xBmHAPdyV/S7Pru2wuJgh6yjlQaVZkpHUxvoZnrp8JSzQvkeObj46kR/6 aMNPZFSKT7MhofXH2fLoLDb20Ge57gEj1+azcapIVlue0TNw62V/fTnEe3P260mFN9X4 btYkpLw1EsuPNntfsnL0vhai3Nlp8ryQKiP4mnflmoqFLBDXXUGhv8JwkdmF7+94lOe8 C7sstKv9CledLTajMzTxI4hBykx/RhA57JCpJsZI1D+vLXiCB2IbQ8DLSPQy/dRyoEXn KQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38wug73v80-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 09:45:29 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 09:45:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 09:45:28 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 2312C3F703F; Wed, 2 Jun 2021 09:45:24 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Archana Muniganti , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Wed, 2 Jun 2021 22:13:36 +0530 Message-ID: <1622652221-22732-16-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622652221-22732-1-git-send-email-anoobj@marvell.com> References: <1622652221-22732-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: le9aemBpdIRJN9lHApDjNvbgXyHDk2GG X-Proofpoint-GUID: le9aemBpdIRJN9lHApDjNvbgXyHDk2GG X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_09:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 15/20] crypto/cnxk: add ZUC and SNOW3G encrypt X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Archana Muniganti Add PDCP opcode which handles ZUC and SNOW3G. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Archana Muniganti Signed-off-by: Tejasree Kondoj --- doc/guides/cryptodevs/features/cn10k.ini | 2 + doc/guides/cryptodevs/features/cn9k.ini | 2 + drivers/crypto/cnxk/cnxk_se.h | 270 ++++++++++++++++++++++++++++++- 3 files changed, 273 insertions(+), 1 deletion(-) diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini index f097d8e..8f20d07 100644 --- a/doc/guides/cryptodevs/features/cn10k.ini +++ b/doc/guides/cryptodevs/features/cn10k.ini @@ -30,6 +30,8 @@ AES CTR (256) = Y AES XTS (128) = Y AES XTS (256) = Y DES CBC = Y +SNOW3G UEA2 = Y +ZUC EEA3 = Y ; ; Supported authentication algorithms of 'cn10k' crypto driver. diff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini index 7007d11..fb0c09b 100644 --- a/doc/guides/cryptodevs/features/cn9k.ini +++ b/doc/guides/cryptodevs/features/cn9k.ini @@ -30,6 +30,8 @@ AES CTR (256) = Y AES XTS (128) = Y AES XTS (256) = Y DES CBC = Y +SNOW3G UEA2 = Y +ZUC EEA3 = Y ; ; Supported authentication algorithms of 'cn9k' crypto driver. diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 6b2e82d..d24b2f3 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -1098,6 +1098,270 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, } static __rte_always_inline int +cpt_zuc_snow3g_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, + struct roc_se_fc_params *params, + struct cpt_inst_s *inst) +{ + uint32_t size; + int32_t inputlen, outputlen; + struct roc_se_ctx *se_ctx; + uint32_t mac_len = 0; + uint8_t pdcp_alg_type, j; + uint32_t encr_offset = 0, auth_offset = 0; + uint32_t encr_data_len = 0, auth_data_len = 0; + int flags, iv_len = 16; + uint64_t offset_ctrl; + uint64_t *offset_vaddr; + uint32_t *iv_s, iv[4]; + union cpt_inst_w4 cpt_inst_w4; + + se_ctx = params->ctx_buf.vaddr; + flags = se_ctx->zsk_flags; + mac_len = se_ctx->mac_len; + pdcp_alg_type = se_ctx->pdcp_alg_type; + + cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G; + + /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ + + cpt_inst_w4.s.opcode_minor = ((1 << 7) | (pdcp_alg_type << 5) | + (0 << 4) | (0 << 3) | (flags & 0x7)); + + if (flags == 0x1) { + /* + * Microcode expects offsets in bytes + * TODO: Rounding off + */ + auth_data_len = ROC_SE_AUTH_DLEN(d_lens); + + /* EIA3 or UIA2 */ + auth_offset = ROC_SE_AUTH_OFFSET(d_offs); + auth_offset = auth_offset / 8; + + /* consider iv len */ + auth_offset += iv_len; + + inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8); + outputlen = mac_len; + + offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset); + + } else { + /* EEA3 or UEA2 */ + /* + * Microcode expects offsets in bytes + * TODO: Rounding off + */ + encr_data_len = ROC_SE_ENCR_DLEN(d_lens); + + encr_offset = ROC_SE_ENCR_OFFSET(d_offs); + encr_offset = encr_offset / 8; + /* consider iv len */ + encr_offset += iv_len; + + inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + + /* iv offset is 0 */ + offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + } + + if (unlikely((encr_offset >> 16) || (auth_offset >> 8))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + CPT_LOG_DP_ERR("auth_offset: %d", auth_offset); + return -1; + } + + /* IV */ + iv_s = (flags == 0x1) ? params->auth_iv_buf : params->iv_buf; + + if (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_SNOW3G) { + /* + * DPDK seems to provide it in form of IV3 IV2 IV1 IV0 + * and BigEndian, MC needs it as IV0 IV1 IV2 IV3 + */ + + for (j = 0; j < 4; j++) + iv[j] = iv_s[3 - j]; + } else { + /* ZUC doesn't need a swap */ + for (j = 0; j < 4; j++) + iv[j] = iv_s[j]; + } + + /* + * GP op header, lengths are expected in bits. + */ + cpt_inst_w4.s.param1 = encr_data_len; + cpt_inst_w4.s.param2 = auth_data_len; + + /* + * In cn9k, cn10k since we have a limitation of + * IV & Offset control word not part of instruction + * and need to be part of Data Buffer, we check if + * head room is there and then only do the Direct mode processing + */ + if (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) && + (req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) { + void *dm_vaddr = params->bufs[0].vaddr; + + /* Use Direct mode */ + + offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - + ROC_SE_OFF_CTRL_LEN - iv_len); + + /* DPTR */ + inst->dptr = (uint64_t)offset_vaddr; + /* RPTR should just exclude offset control word */ + inst->rptr = (uint64_t)dm_vaddr - iv_len; + + cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; + + if (likely(iv_len)) { + uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr + + ROC_SE_OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + } + + *offset_vaddr = offset_ctrl; + } else { + void *m_vaddr = params->meta_buf.vaddr; + uint32_t i, g_size_bytes, s_size_bytes; + struct roc_se_sglist_comp *gather_comp; + struct roc_se_sglist_comp *scatter_comp; + uint8_t *in_buffer; + uint32_t *iv_d; + + /* save space for iv */ + offset_vaddr = m_vaddr; + + m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len; + + cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = + (struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + + i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr, + ROC_SE_OFF_CTRL_LEN + iv_len); + + /* iv offset is 0 */ + *offset_vaddr = offset_ctrl; + + iv_d = (uint32_t *)((uint8_t *)offset_vaddr + + ROC_SE_OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + + /* input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, 0, &size, + NULL, 0); + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", + size); + return -1; + } + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = + ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (struct roc_se_sglist_comp *)((uint8_t *)gather_comp + + g_size_bytes); + + if (flags == 0x1) { + /* IV in SLIST only for EEA3 & UEA2 */ + iv_len = 0; + } + + if (iv_len) { + i = fill_sg_comp(scatter_comp, i, + (uint64_t)offset_vaddr + + ROC_SE_OFF_CTRL_LEN, + iv_len); + } + + /* Add output data */ + if (req_flags & ROC_SE_VALID_MAC_BUF) { + size = outputlen - iv_len - mac_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR( + "Insufficient buffer space," + " size %d needed", + size); + return -1; + } + } + + /* mac data */ + if (mac_len) { + i = fill_sg_comp_from_buf(scatter_comp, i, + ¶ms->mac_buf); + } + } else { + /* Output including mac */ + size = outputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR( + "Insufficient buffer space," + " size %d needed", + size); + return -1; + } + } + } + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = + ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp); + + size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE; + + /* This is DPTR len in case of SG mode */ + cpt_inst_w4.s.dlen = size; + + inst->dptr = (uint64_t)in_buffer; + } + + inst->w4.u64 = cpt_inst_w4.u64; + + return 0; +} + +static __rte_always_inline int cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst) @@ -1124,8 +1388,12 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, fc_type = ctx->fc_type; - if (likely(fc_type == ROC_SE_FC_GEN)) + if (likely(fc_type == ROC_SE_FC_GEN)) { ret = cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, inst); + } else if (fc_type == ROC_SE_PDCP) { + ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, + inst); + } return ret; } -- 2.7.4