From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 46736A0524; Wed, 2 Jun 2021 18:45:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2E133410E6; Wed, 2 Jun 2021 18:44:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D726A410E6 for ; Wed, 2 Jun 2021 18:44:39 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152GaDMi032361; Wed, 2 Jun 2021 09:44:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=V4hKHPtteFUctWY8lJDfUrk4ubR2TyNuS7bNKCIT0K0=; b=YwdBXtd4icJ0tcVKnVAhi2DbB+Vridw/6GGkUg1k65+8vHRAYtAP5XnF+bUNfUUlXVT6 sa9aiTZL4zAU8VQd3X65kFpmY9bKZdxNjucfBYhQi/Du4p0e8hZyjlo3w/KANMD8tVWM E5Ec5eTeYio30kZqHxZhkyS0VC5nzaJ9Ts+Fi74M+luRWY5a2HomX0+1TSTasWQvGHWT J/+E9qzp9AfdW576KC1+AhEioppC+1+TobMokKNMrSaTHnOrdNSJyxq7JSR9llbhq5xF 6jh/raVNjulv8023CSP3Yo3LzNFujsmqovhh5WMfXHGxvz+vAL6MpCpRedBnzbpFvyfG +w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38wufguqxu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 09:44:39 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 09:44:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 09:44:36 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 638E43F703F; Wed, 2 Jun 2021 09:44:32 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , "Ankur Dwivedi" , Tejasree Kondoj , , Archana Muniganti Date: Wed, 2 Jun 2021 22:13:27 +0530 Message-ID: <1622652221-22732-7-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622652221-22732-1-git-send-email-anoobj@marvell.com> References: <1622652221-22732-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: Xi1CxoWtH_y8eV-2IP5MBrGmeP9BLdUS X-Proofpoint-GUID: Xi1CxoWtH_y8eV-2IP5MBrGmeP9BLdUS X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_09:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 06/20] crypto/cnxk: add session ops framework X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add session ops - sym_session_get_size - sym_session_configure - sym_session_clear Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Archana Muniganti Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 6 +- drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 6 +- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 187 ++++++++++++++++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 27 +++++ drivers/crypto/cnxk/cnxk_se.h | 31 +++++ 5 files changed, 251 insertions(+), 6 deletions(-) create mode 100644 drivers/crypto/cnxk/cnxk_se.h diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 007d449..34dc107 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -33,9 +33,9 @@ struct rte_cryptodev_ops cn10k_cpt_ops = { .queue_pair_release = cnxk_cpt_queue_pair_release, /* Symmetric crypto ops */ - .sym_session_get_size = NULL, - .sym_session_configure = NULL, - .sym_session_clear = NULL, + .sym_session_get_size = cnxk_cpt_sym_session_get_size, + .sym_session_configure = cnxk_cpt_sym_session_configure, + .sym_session_clear = cnxk_cpt_sym_session_clear, /* Asymmetric crypto ops */ .asym_session_get_size = NULL, diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index 73ccf5b..bef6159 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -33,9 +33,9 @@ struct rte_cryptodev_ops cn9k_cpt_ops = { .queue_pair_release = cnxk_cpt_queue_pair_release, /* Symmetric crypto ops */ - .sym_session_get_size = NULL, - .sym_session_configure = NULL, - .sym_session_clear = NULL, + .sym_session_get_size = cnxk_cpt_sym_session_get_size, + .sym_session_configure = cnxk_cpt_sym_session_configure, + .sym_session_clear = cnxk_cpt_sym_session_clear, /* Asymmetric crypto ops */ .asym_session_get_size = NULL, diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index d36258b..c2e07cf 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -12,6 +12,7 @@ #include "cnxk_cryptodev.h" #include "cnxk_cryptodev_ops.h" #include "cnxk_cryptodev_capabilities.h" +#include "cnxk_se.h" int cnxk_cpt_dev_config(struct rte_cryptodev *dev, @@ -312,3 +313,189 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, cnxk_cpt_qp_destroy(dev, qp); return ret; } + +unsigned int +cnxk_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) +{ + return sizeof(struct cnxk_se_sess); +} + +static int +sym_xform_verify(struct rte_crypto_sym_xform *xform) +{ + if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && + xform->auth.algo == RTE_CRYPTO_AUTH_NULL && + xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY) + return -ENOTSUP; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL) + return CNXK_CPT_CIPHER; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL) + return CNXK_CPT_AUTH; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD && xform->next == NULL) + return CNXK_CPT_AEAD; + + if (xform->next == NULL) + return -EIO; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && + xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC && + xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH && + xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1) + return -ENOTSUP; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && + xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 && + xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER && + xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC) + return -ENOTSUP; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && + xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT && + xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH && + xform->next->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE) + return CNXK_CPT_CIPHER_ENC_AUTH_GEN; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && + xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY && + xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER && + xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT) + return CNXK_CPT_AUTH_VRFY_CIPHER_DEC; + + if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && + xform->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE && + xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER && + xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) { + switch (xform->auth.algo) { + case RTE_CRYPTO_AUTH_SHA1_HMAC: + switch (xform->next->cipher.algo) { + case RTE_CRYPTO_CIPHER_AES_CBC: + return CNXK_CPT_AUTH_GEN_CIPHER_ENC; + default: + return -ENOTSUP; + } + default: + return -ENOTSUP; + } + } + + if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && + xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT && + xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH && + xform->next->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY) { + switch (xform->cipher.algo) { + case RTE_CRYPTO_CIPHER_AES_CBC: + switch (xform->next->auth.algo) { + case RTE_CRYPTO_AUTH_SHA1_HMAC: + return CNXK_CPT_CIPHER_DEC_AUTH_VRFY; + default: + return -ENOTSUP; + } + default: + return -ENOTSUP; + } + } + + return -ENOTSUP; +} + +static uint64_t +cnxk_cpt_inst_w7_get(struct cnxk_se_sess *sess, struct roc_cpt *roc_cpt) +{ + union cpt_inst_w7 inst_w7; + + inst_w7.s.cptr = (uint64_t)&sess->roc_se_ctx.se_ctx; + + /* Set the engine group */ + if (sess->zsk_flag || sess->chacha_poly) + inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_SE]; + else + inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; + + return inst_w7.u64; +} + +int +sym_session_configure(struct roc_cpt *roc_cpt, int driver_id, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool) +{ + struct cnxk_se_sess *sess_priv; + void *priv; + int ret; + + ret = sym_xform_verify(xform); + if (unlikely(ret < 0)) + return ret; + + if (unlikely(rte_mempool_get(pool, &priv))) { + CPT_LOG_DP_ERR("Could not allocate session private data"); + return -ENOMEM; + } + + memset(priv, 0, sizeof(struct cnxk_se_sess)); + + sess_priv = priv; + + switch (ret) { + default: + ret = -1; + } + + if (ret) + goto priv_put; + + sess_priv->cpt_inst_w7 = cnxk_cpt_inst_w7_get(sess_priv, roc_cpt); + + set_sym_session_private_data(sess, driver_id, sess_priv); + + return 0; + +priv_put: + rte_mempool_put(pool, priv); + + return -ENOTSUP; +} + +int +cnxk_cpt_sym_session_configure(struct rte_cryptodev *dev, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool) +{ + struct cnxk_cpt_vf *vf = dev->data->dev_private; + struct roc_cpt *roc_cpt = &vf->cpt; + uint8_t driver_id; + + driver_id = dev->driver_id; + + return sym_session_configure(roc_cpt, driver_id, xform, sess, pool); +} + +void +sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess) +{ + void *priv = get_sym_session_private_data(sess, driver_id); + struct rte_mempool *pool; + + if (priv == NULL) + return; + + memset(priv, 0, cnxk_cpt_sym_session_get_size(NULL)); + + pool = rte_mempool_from_obj(priv); + + set_sym_session_private_data(sess, driver_id, NULL); + + rte_mempool_put(pool, priv); +} + +void +cnxk_cpt_sym_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_sym_session *sess) +{ + return sym_session_clear(dev->driver_id, sess); +} diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index 96a0f87..8f9b4fe 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -17,6 +17,16 @@ struct cpt_qp_meta_info { int mlen; }; +enum sym_xform_type { + CNXK_CPT_CIPHER = 1, + CNXK_CPT_AUTH, + CNXK_CPT_AEAD, + CNXK_CPT_CIPHER_ENC_AUTH_GEN, + CNXK_CPT_AUTH_VRFY_CIPHER_DEC, + CNXK_CPT_AUTH_GEN_CIPHER_ENC, + CNXK_CPT_CIPHER_DEC_AUTH_VRFY +}; + struct cpt_inflight_req { union cpt_res_s res; struct rte_crypto_op *cop; @@ -70,4 +80,21 @@ int cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, int cnxk_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id); +unsigned int cnxk_cpt_sym_session_get_size(struct rte_cryptodev *dev); + +int cnxk_cpt_sym_session_configure(struct rte_cryptodev *dev, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool); + +int sym_session_configure(struct roc_cpt *roc_cpt, int driver_id, + struct rte_crypto_sym_xform *xform, + struct rte_cryptodev_sym_session *sess, + struct rte_mempool *pool); + +void cnxk_cpt_sym_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_sym_session *sess); + +void sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess); + #endif /* _CNXK_CRYPTODEV_OPS_H_ */ diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h new file mode 100644 index 0000000..9cccab0 --- /dev/null +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _CNXK_SE_H_ +#define _CNXK_SE_H_ +#include + +#include "roc_se.h" + +struct cnxk_se_sess { + uint16_t cpt_op : 4; + uint16_t zsk_flag : 4; + uint16_t aes_gcm : 1; + uint16_t aes_ctr : 1; + uint16_t chacha_poly : 1; + uint16_t is_null : 1; + uint16_t is_gmac : 1; + uint16_t rsvd1 : 3; + uint16_t aad_length; + uint8_t mac_len; + uint8_t iv_length; + uint8_t auth_iv_length; + uint16_t iv_offset; + uint16_t auth_iv_offset; + uint32_t salt; + uint64_t cpt_inst_w7; + struct roc_se_ctx roc_se_ctx; +} __rte_cache_aligned; + +#endif /*_CNXK_SE_H_ */ -- 2.7.4