From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EB59AA0524; Wed, 2 Jun 2021 19:11:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D8F7F410E1; Wed, 2 Jun 2021 19:11:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A6F8F40689 for ; Wed, 2 Jun 2021 19:11:53 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152H6EA6006394; Wed, 2 Jun 2021 10:11:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=hqjCXDEOEHjGy/UTvNayunX/nTfiH0JrTp0gxe/ncro=; b=HXnpvkvHCSDCm66NkQ5Q7DTfv2KW5HSSIGgZxeQK29nS6slDAR3wxzGYzoY9lV89Ytte P4B5XxFjsi7LDJNcoNjEGCYKB2oJkekJ+s24jh92FnmfYytGkPvN/aWA7ksOtkOK2ORp rBs/81gPzF4shiqaNX+DVvPsz7hxUneBRikUOp9jZHHTRNG+IO5ltz0TdM4ccY3bBwlP AiR1HuKEF24upCrzyFN+3gNgzG0Xr7DbXNaJ3hvGCtP0Z2lWBzPWEWk3sh5ki28VD4be Hn9Y3LjZ9WEINwme8/wYzNj5pJOUNWJMVrgFxpKhAILNJFgV0bA7jOXoKFsIhYOVUT/o XA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38wug7404n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 10:11:52 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 10:11:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 10:11:50 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id AE3973F703F; Wed, 2 Jun 2021 10:11:46 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , "Ankur Dwivedi" , Tejasree Kondoj , , Srujana Challa Date: Wed, 2 Jun 2021 22:41:00 +0530 Message-ID: <1622653862-22830-3-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622653862-22830-1-git-send-email-anoobj@marvell.com> References: <1622653862-22830-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 6PdznPkGS6jLvTG7NYZ__ZC69D8Wi5EC X-Proofpoint-GUID: 6PdznPkGS6jLvTG7NYZ__ZC69D8Wi5EC X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_09:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 2/4] crypto/cnxk: add security capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add security capabilities supported by crypto cn10k PMD. Signed-off-by: Anoob Joseph Signed-off-by: Srujana Challa Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cnxk_cryptodev.h | 4 + drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c | 114 ++++++++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_capabilities.h | 9 +- drivers/crypto/cnxk/cnxk_cryptodev_sec.c | 3 +- 4 files changed, 128 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index dcbdc53..1568be3 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -6,6 +6,7 @@ #define _CNXK_CRYPTODEV_H_ #include +#include #include "roc_cpt.h" @@ -31,6 +32,9 @@ struct cnxk_cpt_vf { struct roc_cpt cpt; struct rte_cryptodev_capabilities crypto_caps[CNXK_CPT_MAX_CAPS]; + struct rte_cryptodev_capabilities + sec_crypto_caps[CNXK_SEC_CRYPTO_MAX_CAPS]; + struct rte_security_capability sec_caps[CNXK_SEC_MAX_CAPS]; }; int cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt); diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index e627854..ab37f9c 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -3,6 +3,7 @@ */ #include +#include #include "roc_api.h" @@ -18,6 +19,15 @@ RTE_DIM(caps_##name)); \ } while (0) +#define SEC_CAPS_ADD(cnxk_caps, cur_pos, hw_caps, name) \ + do { \ + if ((hw_caps[CPT_ENG_TYPE_SE].name) || \ + (hw_caps[CPT_ENG_TYPE_IE].name) || \ + (hw_caps[CPT_ENG_TYPE_AE].name)) \ + sec_caps_add(cnxk_caps, cur_pos, sec_caps_##name, \ + RTE_DIM(sec_caps_##name)); \ + } while (0) + static const struct rte_cryptodev_capabilities caps_mul[] = { { /* RSA */ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, @@ -713,6 +723,69 @@ static const struct rte_cryptodev_capabilities caps_end[] = { RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; +static const struct rte_cryptodev_capabilities sec_caps_aes[] = { + { /* AES GCM */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD, + {.aead = { + .algo = RTE_CRYPTO_AEAD_AES_GCM, + .block_size = 16, + .key_size = { + .min = 16, + .max = 32, + .increment = 8 + }, + .digest_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .aad_size = { + .min = 8, + .max = 12, + .increment = 4 + }, + .iv_size = { + .min = 12, + .max = 12, + .increment = 0 + } + }, } + }, } + }, +}; + +static const struct rte_security_capability sec_caps_templ[] = { + { /* IPsec Lookaside Protocol ESP Tunnel Ingress */ + .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL, + .protocol = RTE_SECURITY_PROTOCOL_IPSEC, + .ipsec = { + .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, + .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, + .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS, + .options = { 0 } + }, + .crypto_capabilities = NULL, + .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA + }, + { /* IPsec Lookaside Protocol ESP Tunnel Egress */ + .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL, + .protocol = RTE_SECURITY_PROTOCOL_IPSEC, + .ipsec = { + .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, + .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, + .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS, + .options = { 0 } + }, + .crypto_capabilities = NULL, + .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA + }, + { + .action = RTE_SECURITY_ACTION_TYPE_NONE + } +}; + static void cpt_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos, const struct rte_cryptodev_capabilities *caps, int nb_caps) @@ -748,8 +821,49 @@ cnxk_crypto_capabilities_get(struct cnxk_cpt_vf *vf) return vf->crypto_caps; } +static void +sec_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos, + const struct rte_cryptodev_capabilities *caps, int nb_caps) +{ + if (*cur_pos + nb_caps > CNXK_SEC_CRYPTO_MAX_CAPS) + return; + + memcpy(&cnxk_caps[*cur_pos], caps, nb_caps * sizeof(caps[0])); + *cur_pos += nb_caps; +} + +static void +sec_crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[], + union cpt_eng_caps *hw_caps) +{ + int cur_pos = 0; + + SEC_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, aes); + + sec_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end)); +} + void cnxk_cpt_caps_populate(struct cnxk_cpt_vf *vf) { + unsigned long i; + crypto_caps_populate(vf->crypto_caps, vf->cpt.hw_caps); + sec_crypto_caps_populate(vf->sec_crypto_caps, vf->cpt.hw_caps); + + PLT_STATIC_ASSERT(RTE_DIM(sec_caps_templ) <= RTE_DIM(vf->sec_caps)); + memcpy(vf->sec_caps, sec_caps_templ, sizeof(sec_caps_templ)); + + for (i = 0; i < RTE_DIM(sec_caps_templ) - 1; i++) + vf->sec_caps[i].crypto_capabilities = vf->sec_crypto_caps; +} + +const struct rte_security_capability * +cnxk_crypto_sec_capabilities_get(void *device) +{ + struct rte_cryptodev *dev = device; + struct cnxk_cpt_vf *vf; + + vf = dev->data->dev_private; + return vf->sec_caps; } diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.h b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.h index 85f5ad2..fe07e43 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.h @@ -10,7 +10,7 @@ #include "cnxk_cryptodev.h" /* - * Initialize crypto capabilities for the device + * Initialize crypto and IPsec capabilities for the device * */ void cnxk_cpt_caps_populate(struct cnxk_cpt_vf *vf); @@ -22,4 +22,11 @@ void cnxk_cpt_caps_populate(struct cnxk_cpt_vf *vf); const struct rte_cryptodev_capabilities * cnxk_crypto_capabilities_get(struct cnxk_cpt_vf *vf); +/* + * Get security capabilities list for the device + * + */ +const struct rte_security_capability * +cnxk_crypto_sec_capabilities_get(void *device); + #endif /* _CNXK_CRYPTODEV_CAPABILITIES_H_ */ diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_sec.c b/drivers/crypto/cnxk/cnxk_cryptodev_sec.c index f03d2ed..8d04d4b 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_sec.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_sec.c @@ -7,6 +7,7 @@ #include #include +#include "cnxk_cryptodev_capabilities.h" #include "cnxk_cryptodev_sec.h" /* Common security ops */ @@ -16,7 +17,7 @@ struct rte_security_ops cnxk_sec_ops = { .session_get_size = NULL, .set_pkt_metadata = NULL, .get_userdata = NULL, - .capabilities_get = NULL, + .capabilities_get = cnxk_crypto_sec_capabilities_get }; int -- 2.7.4