From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 825E5A0C40; Fri, 25 Jun 2021 07:37:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9B247410FE; Fri, 25 Jun 2021 07:37:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B5D6D40E46 for ; Fri, 25 Jun 2021 07:37:47 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15P5ZC13014300; Thu, 24 Jun 2021 22:37:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0LJ0uEs6ifnZQuUIAWtqRdZfLyGMdg5jvJ+NRU3IF+c=; b=jkK1m1aU24DwmBfsGMm1eVx5In/uvyVxXmREe9GOxrvIf6fZ0XpPBEiJJUSeElbHuBaW 0fJHY9Zrl/9BD0OJpOudK2SG4hp6vBm+LxWB5PcUIPoxKmsqPs8fKNOeG0qY04iaQ6be wvHGlZD1K8Dil4YVeUJr8FYEhpQ7bHuUezdiY8XBWiK2unXKyPSsaGhmwtwmj6rM8aFj oyHOkab5TGv9kGrX29ACuolThTNiXc9hI6180cYTXZ/lv5S3mQBlrd3xSobhIANbF14u H6wJz9pQoH6yRPuUFxPsCirFlf57AC1v721PJXT2lJK2aobf/dLpBXZVi8vmht5VZWhw Gg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39d241sg58-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Jun 2021 22:37:46 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Jun 2021 22:37:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 24 Jun 2021 22:37:44 -0700 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 2D5EF3F7041; Thu, 24 Jun 2021 22:37:40 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Aakash Sasidharan , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Srujana Challa Date: Fri, 25 Jun 2021 11:06:39 +0530 Message-ID: <1624599410-29689-8-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624599410-29689-1-git-send-email-anoobj@marvell.com> References: <1624599410-29689-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: L-vvKvZw0sPemH-yjixSd1xmA0HJYaYX X-Proofpoint-ORIG-GUID: L-vvKvZw0sPemH-yjixSd1xmA0HJYaYX X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 Subject: [dpdk-dev] [PATCH v2 07/17] common/cnxk: add CPT diagnostics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Aakash Sasidharan Add routines to fetch and dump CPT statistics and states. Signed-off-by: Aakash Sasidharan Signed-off-by: Srujana Challa --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_cpt.c | 29 +++++++ drivers/common/cnxk/roc_cpt.h | 3 + drivers/common/cnxk/roc_cpt_debug.c | 167 ++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 2 + 5 files changed, 202 insertions(+) create mode 100644 drivers/common/cnxk/roc_cpt_debug.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 739e0e4..f139e0b 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -12,6 +12,7 @@ config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( 'roc_cpt.c', + 'roc_cpt_debug.c', 'roc_dev.c', 'roc_idev.c', 'roc_irq.c', diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 02062c1..21c7704 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -188,6 +188,34 @@ cpt_lf_unregister_irqs(struct roc_cpt_lf *lf) cpt_lf_unregister_done_irq(lf); } +static void +cpt_lf_dump(struct roc_cpt_lf *lf) +{ + plt_cpt_dbg("CPT LF"); + plt_cpt_dbg("RBASE: 0x%016" PRIx64, lf->rbase); + plt_cpt_dbg("LMT_BASE: 0x%016" PRIx64, lf->lmt_base); + plt_cpt_dbg("MSIXOFF: 0x%x", lf->msixoff); + plt_cpt_dbg("LF_ID: 0x%x", lf->lf_id); + plt_cpt_dbg("NB DESC: %d", lf->nb_desc); + plt_cpt_dbg("FC_ADDR: 0x%016" PRIx64, (uintptr_t)lf->fc_addr); + plt_cpt_dbg("CQ.VADDR: 0x%016" PRIx64, (uintptr_t)lf->iq_vaddr); + + plt_cpt_dbg("CPT LF REG:"); + plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL, + plt_read64(lf->rbase + CPT_LF_CTL)); + plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG, + plt_read64(lf->rbase + CPT_LF_INPROG)); + + plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE, + plt_read64(lf->rbase + CPT_LF_Q_BASE)); + plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_SIZE, + plt_read64(lf->rbase + CPT_LF_Q_SIZE)); + plt_cpt_dbg("Q_INST_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_INST_PTR, + plt_read64(lf->rbase + CPT_LF_Q_INST_PTR)); + plt_cpt_dbg("Q_GRP_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_GRP_PTR, + plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR)); +} + int roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg) { @@ -484,6 +512,7 @@ cpt_lf_init(struct roc_cpt_lf *lf) if (rc) goto disable_iq; + cpt_lf_dump(lf); return 0; disable_iq: diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index e258ca5..73ecb4e 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -63,5 +63,8 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf); void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf); void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf); +int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); +int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt); void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); + #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c new file mode 100644 index 0000000..9a9dcba --- /dev/null +++ b/drivers/common/cnxk/roc_cpt_debug.c @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +static int +cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct cpt_rd_wr_reg_msg *msg; + struct dev *dev = &cpt->dev; + int ret; + + msg = mbox_alloc_msg_cpt_rd_wr_register(dev->mbox); + if (msg == NULL) + return -EIO; + + msg->hdr.pcifunc = dev->pf_func; + + msg->is_write = 0; + msg->reg_offset = reg; + msg->ret_val = val; + + ret = mbox_process_msg(dev->mbox, (void *)&msg); + if (ret) + return -EIO; + + *val = msg->val; + + return 0; +} + +static int +cpt_sts_print(struct roc_cpt *roc_cpt) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct dev *dev = &cpt->dev; + struct cpt_sts_req *req; + struct cpt_sts_rsp *rsp; + int ret; + + req = mbox_alloc_msg_cpt_sts_get(dev->mbox); + if (req == NULL) + return -EIO; + + req->blkaddr = 0; + ret = mbox_process_msg(dev->mbox, (void *)&rsp); + if (ret) + return -EIO; + + plt_print(" %s:\t0x%016" PRIx64, "inst_req_pc", rsp->inst_req_pc); + plt_print(" %s:\t0x%016" PRIx64, "inst_lat_pc", rsp->inst_lat_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "rd_req_pc", rsp->rd_req_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "rd_lat_pc", rsp->rd_lat_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "rd_uc_pc", rsp->rd_uc_pc); + plt_print(" %s:\t0x%016" PRIx64, "active_cycles_pc", + rsp->active_cycles_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "ctx_mis_pc", rsp->ctx_mis_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "ctx_hit_pc", rsp->ctx_hit_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "ctx_aop_pc", rsp->ctx_aop_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_aop_lat_pc", + rsp->ctx_aop_lat_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_ifetch_pc", + rsp->ctx_ifetch_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_ifetch_lat_pc", + rsp->ctx_ifetch_lat_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_ffetch_pc", + rsp->ctx_ffetch_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_ffetch_lat_pc", + rsp->ctx_ffetch_lat_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_wback_pc", rsp->ctx_wback_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_wback_lat_pc", + rsp->ctx_wback_lat_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "ctx_psh_pc", rsp->ctx_psh_pc); + plt_print(" %s:\t0x%016" PRIx64, "ctx_psh_lat_pc", + rsp->ctx_psh_lat_pc); + plt_print(" %s:\t\t0x%016" PRIx64, "ctx_err", rsp->ctx_err); + plt_print(" %s:\t\t0x%016" PRIx64, "ctx_enc_id", rsp->ctx_enc_id); + plt_print(" %s:\t0x%016" PRIx64, "ctx_flush_timer", + rsp->ctx_flush_timer); + plt_print(" %s:\t\t0x%016" PRIx64, "rxc_time", rsp->rxc_time); + plt_print(" %s:\t0x%016" PRIx64, "rxc_time_cfg", rsp->rxc_time_cfg); + plt_print(" %s:\t0x%016" PRIx64, "rxc_active_sts", + rsp->rxc_active_sts); + plt_print(" %s:\t0x%016" PRIx64, "rxc_zombie_sts", + rsp->rxc_zombie_sts); + plt_print(" %s:\t0x%016" PRIx64, "rxc_dfrg", rsp->rxc_dfrg); + plt_print(" %s:\t0x%016" PRIx64, "x2p_link_cfg0", + rsp->x2p_link_cfg0); + plt_print(" %s:\t0x%016" PRIx64, "x2p_link_cfg1", + rsp->x2p_link_cfg1); + plt_print(" %s:\t0x%016" PRIx64, "busy_sts_ae", rsp->busy_sts_ae); + plt_print(" %s:\t0x%016" PRIx64, "free_sts_ae", rsp->free_sts_ae); + plt_print(" %s:\t0x%016" PRIx64, "busy_sts_se", rsp->busy_sts_se); + plt_print(" %s:\t0x%016" PRIx64, "free_sts_se", rsp->free_sts_se); + plt_print(" %s:\t0x%016" PRIx64, "busy_sts_ie", rsp->busy_sts_ie); + plt_print(" %s:\t0x%016" PRIx64, "free_sts_ie", rsp->free_sts_ie); + plt_print(" %s:\t0x%016" PRIx64, "exe_err_info", rsp->exe_err_info); + plt_print(" %s:\t\t0x%016" PRIx64, "cptclk_cnt", rsp->cptclk_cnt); + plt_print(" %s:\t\t0x%016" PRIx64, "diag", rsp->diag); + + return 0; +} + +int +roc_cpt_afs_print(struct roc_cpt *roc_cpt) +{ + uint64_t reg_val; + + plt_print("CPT AF registers:"); + + if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL(0), ®_val)) + return -EIO; + + plt_print(" CPT_AF_LF0_CTL:\t0x%016" PRIx64, reg_val); + + if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL2(0), ®_val)) + return -EIO; + + plt_print(" CPT_AF_LF0_CTL2:\t0x%016" PRIx64, reg_val); + + cpt_sts_print(roc_cpt); + + return 0; +} + +static void +cpt_lf_print(struct roc_cpt_lf *lf) +{ + uint64_t reg_val; + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT); + plt_print(" Encrypted byte count:\t%" PRIu64, reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT); + plt_print(" Encrypted packet count:\t%" PRIu64, reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT); + plt_print(" Decrypted byte count:\t%" PRIu64, reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT); + plt_print(" Decrypted packet count:\t%" PRIu64, reg_val); +} + +int +roc_cpt_lfs_print(struct roc_cpt *roc_cpt) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct roc_cpt_lf *lf; + int lf_id; + + if (cpt == NULL) + return -EINVAL; + + for (lf_id = 0; lf_id < roc_cpt->nb_lf; lf_id++) { + lf = roc_cpt->lf[lf_id]; + if (lf == NULL) + continue; + + plt_print("Count registers for CPT LF%d:", lf_id); + cpt_lf_print(lf); + } + + return 0; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 128997e..87130df 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -11,6 +11,7 @@ INTERNAL { cnxk_logtype_tim; cnxk_logtype_tm; roc_clk_freq_get; + roc_cpt_afs_print; roc_cpt_dev_clear; roc_cpt_dev_configure; roc_cpt_dev_fini; @@ -19,6 +20,7 @@ INTERNAL { roc_cpt_iq_disable; roc_cpt_lf_init; roc_cpt_lf_fini; + roc_cpt_lfs_print; roc_cpt_rxc_time_cfg; roc_error_msg_get; roc_idev_cpt_get; -- 2.7.4