From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D40A7A0C40; Fri, 25 Jun 2021 07:57:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DF32740E5A; Fri, 25 Jun 2021 07:57:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5AD2E40698 for ; Fri, 25 Jun 2021 07:57:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15P5vCah018115; Thu, 24 Jun 2021 22:57:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZrkikovJUwIjSD5t5EInBUGW6bJwD/1z7cKO3XeFFWA=; b=POKUsdu1ht+HvMmjKpnqq+6QvjDKdoFol7BzztYDq4k/mrEKtCFDY9JM/jHENSJcjgJe yQqRzAb3t3gtRBhisZvS7McbJ0l0u2rUW4M4KoxNRZ19irk1ksjVYZUWqqkGs0kUoOBm SqimFztbm0iEI5+MNu/K5Fe3IXgJge354314udMpeRcRQIbcg5df41ngq5hiW5iYvayj T+K2+HWCXefq9Qzy7A5hQlGKScdR2ovmDVQy+dEFr/vq6EPnxtLYW8tReyeqpUxVZbKj ZkNQu2ddNWQqOFV5kPU4OaIkhnppveGbRv0uIV9npV/SFOOvuDYAWfjP15M1D3y0RX4j oA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39d241shnv-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Jun 2021 22:57:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Jun 2021 22:57:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 24 Jun 2021 22:57:07 -0700 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id B13063F7041; Thu, 24 Jun 2021 22:57:04 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Ankur Dwivedi , Jerin Jacob , Tejasree Kondoj , , Anoob Joseph , Archana Muniganti Date: Fri, 25 Jun 2021 11:26:12 +0530 Message-ID: <1624600591-29841-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624600591-29841-1-git-send-email-anoobj@marvell.com> References: <1624600591-29841-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 35MQEnr7Zyc8jLHjJu-vV3NpEt35VtDT X-Proofpoint-ORIG-GUID: 35MQEnr7Zyc8jLHjJu-vV3NpEt35VtDT X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_02:2021-06-24, 2021-06-25 signatures=0 Subject: [dpdk-dev] [PATCH v2 01/20] crypto/cnxk: add driver skeleton X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ankur Dwivedi Add driver skeleton for crypto_cn9k & crypto_cn10k PMDs leveraging cnxk common framework. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Archana Muniganti Signed-off-by: Tejasree Kondoj --- MAINTAINERS | 9 +++ doc/guides/cryptodevs/cnxk.rst | 126 +++++++++++++++++++++++++++++++ doc/guides/cryptodevs/features/cn10k.ini | 21 ++++++ doc/guides/cryptodevs/features/cn9k.ini | 21 ++++++ drivers/crypto/cnxk/cn10k_cryptodev.c | 42 +++++++++++ drivers/crypto/cnxk/cn10k_cryptodev.h | 13 ++++ drivers/crypto/cnxk/cn9k_cryptodev.c | 40 ++++++++++ drivers/crypto/cnxk/cn9k_cryptodev.h | 13 ++++ drivers/crypto/cnxk/meson.build | 16 ++++ drivers/crypto/cnxk/version.map | 3 + drivers/crypto/meson.build | 1 + 11 files changed, 305 insertions(+) create mode 100644 doc/guides/cryptodevs/cnxk.rst create mode 100644 doc/guides/cryptodevs/features/cn10k.ini create mode 100644 doc/guides/cryptodevs/features/cn9k.ini create mode 100644 drivers/crypto/cnxk/cn10k_cryptodev.c create mode 100644 drivers/crypto/cnxk/cn10k_cryptodev.h create mode 100644 drivers/crypto/cnxk/cn9k_cryptodev.c create mode 100644 drivers/crypto/cnxk/cn9k_cryptodev.h create mode 100644 drivers/crypto/cnxk/meson.build create mode 100644 drivers/crypto/cnxk/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 5877a16..851b408 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1080,6 +1080,15 @@ F: drivers/crypto/octeontx2/ F: doc/guides/cryptodevs/octeontx2.rst F: doc/guides/cryptodevs/features/octeontx2.ini +Marvell cnxk crypto +M: Ankur Dwivedi +M: Anoob Joseph +M: Tejasree Kondoj +F: drivers/crypto/cnxk/ +F: doc/guides/cryptodevs/cnxk.rst +F: doc/guides/cryptodevs/features/cn9k.ini +F: doc/guides/cryptodevs/features/cn10k.ini + Null Crypto M: Declan Doherty F: drivers/crypto/null/ diff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst new file mode 100644 index 0000000..8bac539 --- /dev/null +++ b/doc/guides/cryptodevs/cnxk.rst @@ -0,0 +1,126 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2021 Marvell. + +Marvell cnxk Crypto Poll Mode Driver +==================================== + +The cnxk crypto poll mode driver provides support for offloading +cryptographic operations to cryptographic accelerator units on the +**Marvell OCTEON cnxk** SoC family. + +The cnxk crypto PMD code is organized into different sets of files. +The file names starting with cn9k and cn10k provides support for CN9XX +and CN10XX respectively. The common code between the SoCs is present +in file names starting with cnxk. + +More information about OCTEON cnxk SoCs may be obtained from ``_ + +Supported OCTEON cnxk SoCs +-------------------------- + +- CN9XX +- CN10XX + +Installation +------------ + +The OCTEON cnxk crypto PMD may be compiled natively on an OCTEON cnxk platform +or cross-compiled on an x86 platform. + +Refer to :doc:`../platform/cnxk` for instructions to build your DPDK +application. + +.. note:: + + The OCTEON cnxk crypto PMD uses services from the kernel mode OCTEON cnxk + crypto PF driver in linux. This driver is included in the OCTEON TX SDK. + +Initialization +-------------- + +``CN9K Initialization`` + +List the CPT PF devices available on cn9k platform: + +.. code-block:: console + + lspci -d:a0fd + +``a0fd`` is the CPT PF device id. You should see output similar to: + +.. code-block:: console + + 0002:10:00.0 Class 1080: Device 177d:a0fd + +Set ``sriov_numvfs`` on the CPT PF device, to create a VF: + +.. code-block:: console + + echo 1 > /sys/bus/pci/devices/0002:10:00.0/sriov_numvfs + +Bind the CPT VF device to the vfio_pci driver: + +.. code-block:: console + + cd + ./usertools/dpdk-devbind.py -u 0002:10:00.1 + ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1 + +.. note:: + + * For CN98xx SoC, it is recommended to use even and odd DBDF VFs to achieve + higher performance as even VF uses one crypto engine and odd one uses + another crypto engine. + + * Ensure that sufficient huge pages are available for your application:: + + dpdk-hugepages.py --setup 4G --pagesize 512M + + Refer to :ref:`linux_gsg_hugepages` for more details. + +``CN10K Initialization`` + +List the CPT PF devices available on cn10k platform: + +.. code-block:: console + + lspci -d:a0f2 + +``a0f2`` is the CPT PF device id. You should see output similar to: + +.. code-block:: console + + 0002:20:00.0 Class 1080: Device 177d:a0f2 + +Set ``sriov_numvfs`` on the CPT PF device, to create a VF: + +.. code-block:: console + + echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs + +Bind the CPT VF device to the vfio_pci driver: + +.. code-block:: console + + cd + ./usertools/dpdk-devbind.py -u 0002:20:00.1 + ./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1 + +Debugging Options +----------------- + +.. _table_octeon_cnxk_crypto_debug_options: + +.. table:: OCTEON cnxk crypto PMD debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | CPT | --log-level='pmd\.crypto\.cnxk,8' | + +---+------------+-------------------------------------------------------+ + +Limitations +----------- + +Multiple lcores may not operate on the same crypto queue pair. The lcore that +enqueues to a queue pair is the one that must dequeue from it. diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini new file mode 100644 index 0000000..0aa097d --- /dev/null +++ b/doc/guides/cryptodevs/features/cn10k.ini @@ -0,0 +1,21 @@ +; +; Supported features of the 'cn10k' crypto driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] + +; +; Supported crypto algorithms of 'cn10k' crypto driver. +; +[Cipher] + +; +; Supported authentication algorithms of 'cn10k' crypto driver. +; +[Auth] + +; +; Supported AEAD algorithms of 'cn10k' crypto driver. +; +[AEAD] diff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini new file mode 100644 index 0000000..64ee929 --- /dev/null +++ b/doc/guides/cryptodevs/features/cn9k.ini @@ -0,0 +1,21 @@ +; +; Supported features of the 'cn9k' crypto driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] + +; +; Supported crypto algorithms of 'cn9k' crypto driver. +; +[Cipher] + +; +; Supported authentication algorithms of 'cn9k' crypto driver. +; +[Auth] + +; +; Supported AEAD algorithms of 'cn9k' crypto driver. +; +[AEAD] diff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c new file mode 100644 index 0000000..4d2140c --- /dev/null +++ b/drivers/crypto/cnxk/cn10k_cryptodev.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cn10k_cryptodev.h" +#include "roc_api.h" + +uint8_t cn10k_cryptodev_driver_id; + +static struct rte_pci_id pci_id_cpt_table[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, + PCI_DEVID_CN10K_RVU_CPT_VF) + }, + /* sentinel */ + { + .device_id = 0 + }, +}; + +static struct rte_pci_driver cn10k_cryptodev_pmd = { + .id_table = pci_id_cpt_table, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = NULL, + .remove = NULL, +}; + +static struct cryptodev_driver cn10k_cryptodev_drv; + +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CN10K_PMD, cn10k_cryptodev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CN10K_PMD, pci_id_cpt_table); +RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_CN10K_PMD, "vfio-pci"); +RTE_PMD_REGISTER_CRYPTO_DRIVER(cn10k_cryptodev_drv, cn10k_cryptodev_pmd.driver, + cn10k_cryptodev_driver_id); diff --git a/drivers/crypto/cnxk/cn10k_cryptodev.h b/drivers/crypto/cnxk/cn10k_cryptodev.h new file mode 100644 index 0000000..61f62ef --- /dev/null +++ b/drivers/crypto/cnxk/cn10k_cryptodev.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _CN10K_CRYPTODEV_H_ +#define _CN10K_CRYPTODEV_H_ + +/* Marvell OCTEON CN10K Crypto PMD device name */ +#define CRYPTODEV_NAME_CN10K_PMD crypto_cn10k + +extern uint8_t cn10k_cryptodev_driver_id; + +#endif /* _CN10K_CRYPTODEV_H_ */ diff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c new file mode 100644 index 0000000..7654c53 --- /dev/null +++ b/drivers/crypto/cnxk/cn9k_cryptodev.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cn9k_cryptodev.h" +#include "roc_api.h" + +uint8_t cn9k_cryptodev_driver_id; + +static struct rte_pci_id pci_id_cpt_table[] = { + { + }, + /* sentinel */ + { + .device_id = 0 + }, +}; + +static struct rte_pci_driver cn9k_cryptodev_pmd = { + .id_table = pci_id_cpt_table, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = NULL, + .remove = NULL, +}; + +static struct cryptodev_driver cn9k_cryptodev_drv; + +RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CN9K_PMD, cn9k_cryptodev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CN9K_PMD, pci_id_cpt_table); +RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_CN9K_PMD, "vfio-pci"); +RTE_PMD_REGISTER_CRYPTO_DRIVER(cn9k_cryptodev_drv, cn9k_cryptodev_pmd.driver, + cn9k_cryptodev_driver_id); diff --git a/drivers/crypto/cnxk/cn9k_cryptodev.h b/drivers/crypto/cnxk/cn9k_cryptodev.h new file mode 100644 index 0000000..f6e7965 --- /dev/null +++ b/drivers/crypto/cnxk/cn9k_cryptodev.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _CN9K_CRYPTODEV_H_ +#define _CN9K_CRYPTODEV_H_ + +/* Marvell OCTEON CN9K Crypto PMD device name */ +#define CRYPTODEV_NAME_CN9K_PMD crypto_cn9k + +extern uint8_t cn9k_cryptodev_driver_id; + +#endif /* _CN9K_CRYPTODEV_H_ */ diff --git a/drivers/crypto/cnxk/meson.build b/drivers/crypto/cnxk/meson.build new file mode 100644 index 0000000..197b94c --- /dev/null +++ b/drivers/crypto/cnxk/meson.build @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2021 Marvell. +# + +if not is_linux or not dpdk_conf.get('RTE_ARCH_64') + build = false + reason = 'only supported on 64-bit Linux' + subdir_done() +endif + +sources = files( + 'cn9k_cryptodev.c', + 'cn10k_cryptodev.c', +) + +deps += ['bus_pci', 'common_cnxk'] diff --git a/drivers/crypto/cnxk/version.map b/drivers/crypto/cnxk/version.map new file mode 100644 index 0000000..ee80c51 --- /dev/null +++ b/drivers/crypto/cnxk/version.map @@ -0,0 +1,3 @@ +INTERNAL { + local: *; +}; diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index b9fdf93..cb865aa 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -12,6 +12,7 @@ drivers = [ 'bcmfs', 'caam_jr', 'ccp', + 'cnxk', 'dpaa_sec', 'dpaa2_sec', 'kasumi', -- 2.7.4