From: <skoteshwar@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>
Cc: <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH v2 6/8] common/cnxk: set of handlers to get tm hierarchy internals
Date: Sat, 18 Sep 2021 10:31:56 -0400 [thread overview]
Message-ID: <1631975519-30924-7-git-send-email-skoteshwar@marvell.com> (raw)
In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com>
From: Satha Rao <skoteshwar@marvell.com>
Platform specific TM tree hierarchy details are part of common cnxk
driver. This patch introduces missing HAL apis to return state of
TM hierarchy required to support ethdev TM operations inside cnxk PMD.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
drivers/common/cnxk/roc_model.h | 6 +++
drivers/common/cnxk/roc_nix.h | 10 ++++
drivers/common/cnxk/roc_nix_priv.h | 1 -
drivers/common/cnxk/roc_nix_tm.c | 22 ++++++++-
drivers/common/cnxk/roc_nix_tm_ops.c | 11 +----
drivers/common/cnxk/roc_nix_tm_utils.c | 86 ++++++++++++++++++++++++++++++++--
drivers/common/cnxk/version.map | 8 ++++
7 files changed, 127 insertions(+), 17 deletions(-)
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index c1d11b7..856a570 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -106,6 +106,12 @@ struct roc_model {
}
static inline uint64_t
+roc_model_is_cn96_cx(void)
+{
+ return (roc_model->flag & ROC_MODEL_CN96xx_C0);
+}
+
+static inline uint64_t
roc_model_is_cn95_a0(void)
{
return roc_model->flag & ROC_MODEL_CNF95xx_A0;
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 90dc413..d9a4613 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -490,6 +490,16 @@ int __roc_api roc_nix_tm_node_name_get(struct roc_nix *roc_nix,
uint32_t node_id, char *buf,
size_t buflen);
int __roc_api roc_nix_smq_flush(struct roc_nix *roc_nix);
+int __roc_api roc_nix_tm_max_prio(struct roc_nix *roc_nix, int lvl);
+int __roc_api roc_nix_tm_lvl_is_leaf(struct roc_nix *roc_nix, int lvl);
+void __roc_api
+roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node,
+ struct roc_nix_tm_shaper_profile *profile);
+int __roc_api roc_nix_tm_lvl_cnt_get(struct roc_nix *roc_nix);
+int __roc_api roc_nix_tm_lvl_have_link_access(struct roc_nix *roc_nix, int lvl);
+int __roc_api roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix);
+bool __roc_api roc_nix_tm_is_user_hierarchy_enabled(struct roc_nix *nix);
+int __roc_api roc_nix_tm_tree_type_get(struct roc_nix *nix);
/* MAC */
int __roc_api roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start);
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index 3412bf2..b67f648 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -350,7 +350,6 @@ int nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,
int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);
int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,
bool rr_quantum_only);
-int nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix);
/*
* TM priv utils.
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 947320a..08d6e86 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -155,6 +155,20 @@
return 0;
}
+static int
+nix_tm_root_node_get(struct nix *nix, int tree)
+{
+ struct nix_tm_node_list *list = nix_tm_node_list(nix, tree);
+ struct nix_tm_node *tm_node;
+
+ TAILQ_FOREACH(tm_node, list, node) {
+ if (tm_node->hw_lvl == nix->tm_root_lvl)
+ return 1;
+ }
+
+ return 0;
+}
+
int
nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)
{
@@ -207,6 +221,10 @@
if (nix_tm_node_search(nix, node_id, tree))
return NIX_ERR_TM_NODE_EXISTS;
+ /* Check if root node exists */
+ if (hw_lvl == nix->tm_root_lvl && nix_tm_root_node_get(nix, tree))
+ return NIX_ERR_TM_NODE_EXISTS;
+
profile = nix_tm_shaper_profile_search(nix, profile_id);
if (!nix_tm_is_leaf(nix, lvl)) {
/* Check if shaper profile exists for non leaf node */
@@ -1157,7 +1175,7 @@
}
int
-nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)
+roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)
{
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
uint32_t nonleaf_id = nix->nb_tx_queues;
@@ -1227,7 +1245,7 @@
goto error;
node->id = i;
- node->parent_id = parent;
+ node->parent_id = parent + i;
node->priority = 0;
node->weight = NIX_TM_DFLT_RR_WT;
node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index 69d5837..29f276a 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -927,13 +927,6 @@
return rc;
}
- /* Prepare rlimit tree */
- rc = nix_tm_prepare_rate_limited_tree(roc_nix);
- if (rc) {
- plt_err("failed to prepare rlimit tm tree, rc=%d", rc);
- return rc;
- }
-
return rc;
}
@@ -951,11 +944,11 @@
uint8_t k = 0;
int rc;
- if (nix->tm_tree != ROC_NIX_TM_RLIMIT ||
+ if ((nix->tm_tree == ROC_NIX_TM_USER) ||
!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))
return NIX_ERR_TM_INVALID_TREE;
- node = nix_tm_node_search(nix, qid, ROC_NIX_TM_RLIMIT);
+ node = nix_tm_node_search(nix, qid, nix->tm_tree);
/* check if we found a valid leaf node */
if (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||
diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 8330624..a135454 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -235,6 +235,9 @@ struct nix_tm_node *
struct nix_tm_shaper_data *cir,
struct nix_tm_shaper_data *pir)
{
+ memset(cir, 0, sizeof(*cir));
+ memset(pir, 0, sizeof(*pir));
+
if (!profile)
return;
@@ -624,8 +627,6 @@ struct nix_tm_node *
uint64_t adjust = 0;
uint8_t k = 0;
- memset(&cir, 0, sizeof(cir));
- memset(&pir, 0, sizeof(pir));
nix_tm_shaper_conf_get(profile, &cir, &pir);
if (profile && node->pkt_mode)
@@ -1043,15 +1044,16 @@ struct nix_tm_shaper_profile *
if (node->hw_lvl != NIX_TXSCH_LVL_TL1)
return NIX_ERR_OP_NOTSUP;
+ /* Check if node has HW resource */
+ if (!(node->flags & NIX_TM_NODE_HWRES))
+ return 0;
+
schq = node->hw_id;
/* Skip fetch if not requested */
if (!n_stats)
goto clear_stats;
memset(n_stats, 0, sizeof(struct roc_nix_tm_node_stats));
- /* Check if node has HW resource */
- if (!(node->flags & NIX_TM_NODE_HWRES))
- return 0;
req = mbox_alloc_msg_nix_txschq_cfg(mbox);
req->read = 1;
@@ -1102,3 +1104,77 @@ struct nix_tm_shaper_profile *
return mbox_process_msg(mbox, (void **)&rsp);
}
+
+bool
+roc_nix_tm_is_user_hierarchy_enabled(struct roc_nix *roc_nix)
+{
+ struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+
+ if ((nix->tm_flags & NIX_TM_HIERARCHY_ENA) &&
+ (nix->tm_tree == ROC_NIX_TM_USER))
+ return true;
+ return false;
+}
+
+int
+roc_nix_tm_tree_type_get(struct roc_nix *roc_nix)
+{
+ struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+
+ return nix->tm_tree;
+}
+
+int
+roc_nix_tm_max_prio(struct roc_nix *roc_nix, int lvl)
+{
+ struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+ int hw_lvl = nix_tm_lvl2nix(nix, lvl);
+
+ return nix_tm_max_prio(nix, hw_lvl);
+}
+
+int
+roc_nix_tm_lvl_is_leaf(struct roc_nix *roc_nix, int lvl)
+{
+ return nix_tm_is_leaf(roc_nix_to_nix_priv(roc_nix), lvl);
+}
+
+void
+roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node,
+ struct roc_nix_tm_shaper_profile *roc_prof)
+{
+ struct nix_tm_node *tm_node = (struct nix_tm_node *)node;
+ struct nix_tm_shaper_profile *profile;
+ struct nix_tm_shaper_data cir, pir;
+
+ profile = (struct nix_tm_shaper_profile *)roc_prof->reserved;
+ tm_node->red_algo = NIX_REDALG_STD;
+
+ /* C0 doesn't support STALL when both PIR & CIR are enabled */
+ if (profile && roc_model_is_cn96_cx()) {
+ nix_tm_shaper_conf_get(profile, &cir, &pir);
+
+ if (pir.rate && cir.rate)
+ tm_node->red_algo = NIX_REDALG_DISCARD;
+ }
+}
+
+int
+roc_nix_tm_lvl_cnt_get(struct roc_nix *roc_nix)
+{
+ if (nix_tm_have_tl1_access(roc_nix_to_nix_priv(roc_nix)))
+ return NIX_TXSCH_LVL_CNT;
+
+ return (NIX_TXSCH_LVL_CNT - 1);
+}
+
+int
+roc_nix_tm_lvl_have_link_access(struct roc_nix *roc_nix, int lvl)
+{
+ struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+
+ if (nix_tm_lvl2nix(nix, lvl) == NIX_TXSCH_LVL_TL1)
+ return 1;
+
+ return 0;
+}
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 776cabb..9b7cbf6 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -175,10 +175,16 @@ INTERNAL {
roc_nix_tm_err_to_rte_err;
roc_nix_tm_fini;
roc_nix_tm_free_resources;
+ roc_nix_tm_lvl_cnt_get;
+ roc_nix_tm_tree_type_get;
roc_nix_tm_hierarchy_disable;
roc_nix_tm_hierarchy_enable;
roc_nix_tm_init;
+ roc_nix_tm_is_user_hierarchy_enabled;
roc_nix_tm_leaf_cnt;
+ roc_nix_tm_lvl_have_link_access;
+ roc_nix_tm_lvl_is_leaf;
+ roc_nix_tm_max_prio;
roc_nix_tm_node_add;
roc_nix_tm_node_delete;
roc_nix_tm_node_get;
@@ -191,10 +197,12 @@ INTERNAL {
roc_nix_tm_node_stats_get;
roc_nix_tm_node_suspend_resume;
roc_nix_tm_prealloc_res;
+ roc_nix_tm_prepare_rate_limited_tree;
roc_nix_tm_rlimit_sq;
roc_nix_tm_root_has_sp;
roc_nix_tm_rsrc_count;
roc_nix_tm_rsrc_max;
+ roc_nix_tm_shaper_default_red_algo;
roc_nix_tm_shaper_profile_add;
roc_nix_tm_shaper_profile_delete;
roc_nix_tm_shaper_profile_get;
--
1.8.3.1
next prev parent reply other threads:[~2021-09-18 14:32 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 17:10 [dpdk-dev] [PATCH 1/8] common/cnxk: use different macros for sdp and lbk max frames skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 2/8] common/cnxk: flush smq skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 3/8] common/cnxk: increase sched weight and shaper burst limit skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 4/8] common/cnxk: handle packet mode shaper limits skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 5/8] common/cnxk: handler to get rte tm error type skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 6/8] common/cnxk: set of handlers to get tm hierarchy internals skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 7/8] net/cnxk: tm capabilities and queue rate limit handlers skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 8/8] net/cnxk: tm shaper and node operations skoteshwar
2021-09-16 7:17 ` [dpdk-dev] [PATCH 1/8] common/cnxk: use different macros for sdp and lbk max frames Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 0/8] Add TM Support for CN9K and CN10K skoteshwar
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 1/8] common/cnxk: use different macros for sdp and lbk max frames skoteshwar
2021-09-21 6:35 ` Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 2/8] common/cnxk: flush smq skoteshwar
2021-09-21 6:37 ` Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 3/8] common/cnxk: increase sched weight and shaper burst limit skoteshwar
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 4/8] common/cnxk: handle packet mode shaper limits skoteshwar
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 5/8] common/cnxk: handler to get rte tm error type skoteshwar
2021-09-21 6:41 ` Jerin Jacob
2021-09-18 14:31 ` skoteshwar [this message]
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 7/8] net/cnxk: tm capabilities and queue rate limit handlers skoteshwar
2021-09-21 6:43 ` Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 8/8] net/cnxk: tm shaper and node operations skoteshwar
2021-09-20 8:59 ` [dpdk-dev] [PATCH v2 0/8] Add TM Support for CN9K and CN10K nithind1988
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 " skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 1/8] common/cnxk: set appropriate max frame size for SDP and LBK skoteshwar
2021-09-27 13:29 ` Jerin Jacob
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 2/8] common/cnxk: support SMQ flush skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 3/8] common/cnxk: increase sched weight and shaper burst limit skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 4/8] common/cnxk: handle packet mode shaper limits skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 5/8] common/cnxk: support TM error type get skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 6/8] common/cnxk: set of handlers to get TM hierarchy internals skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 7/8] net/cnxk: TM capabilities and queue rate limit handlers skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 8/8] net/cnxk: TM shaper and node operations skoteshwar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1631975519-30924-7-git-send-email-skoteshwar@marvell.com \
--to=skoteshwar@marvell.com \
--cc=dev@dpdk.org \
--cc=kirankumark@marvell.com \
--cc=mdr@ashroe.eu \
--cc=ndabilpuram@marvell.com \
--cc=skori@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).