From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0ACDA034F; Tue, 7 Dec 2021 07:52:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C2F94274B; Tue, 7 Dec 2021 07:52:09 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0097542746 for ; Tue, 7 Dec 2021 07:52:06 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1B76pJvp018306 for ; Mon, 6 Dec 2021 22:52:06 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5GwSRc8BoA26PYkHnz4TPvh9+T48FBa6dOhOzSMvqPU=; b=h3Ghz+ut86TsxwjAjKtlxIDy0+9EJKW/O+EEz6Xj5zOPCOJXPGPHgQi07C4uz4Pr2bh3 CB/DOJwyqDjljTk1vZv/+jdTrOFYq2Zq7sTkegLXHV1PpAFLCm47phlmRLF+N4uXto21 4wnefjEJdmZlldr9SB9g40Hp7vcOR7P4HVa9utdjPr5Eo6Y/w8U0IIjMaEIevQMPpsUV XJ/GlGSp12Gv1KBCTm6et7ql0ndU6u7F4bCgGlJociiRneTCrrarKLoPPhXsi6y9UahE gr9rHZmbX3/w5M/oQPOwR8WO520VTHWUVMr4xMLZ5TZ1iVGp+/JhuIeErAZKzU1zyFFA fw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ct2q9004x-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 06 Dec 2021 22:52:06 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 6 Dec 2021 22:51:17 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 6 Dec 2021 22:51:17 -0800 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 0B4E93F7092; Mon, 6 Dec 2021 22:51:14 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Archana Muniganti , Tejasree Kondoj , Subject: [PATCH 03/25] common/cnxk: add bit fields for params Date: Tue, 7 Dec 2021 12:20:36 +0530 Message-ID: <1638859858-734-4-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1638859858-734-1-git-send-email-anoobj@marvell.com> References: <1638859858-734-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 7EosAr02vMxB05q1-PyBP4jXLRD8Zs5D X-Proofpoint-ORIG-GUID: 7EosAr02vMxB05q1-PyBP4jXLRD8Zs5D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-07_02,2021-12-06_02,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Archana Muniganti Added new structure with bit fields for params. Signed-off-by: Archana Muniganti --- drivers/common/cnxk/roc_ie_on.h | 30 +++++++++++++++++++++++++++++- drivers/crypto/cnxk/cn9k_ipsec.c | 16 +++++++++++++--- 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h index 53591c6..817ef33 100644 --- a/drivers/common/cnxk/roc_ie_on.h +++ b/drivers/common/cnxk/roc_ie_on.h @@ -21,7 +21,6 @@ enum roc_ie_on_ucc_ipsec { }; /* Helper macros */ -#define ROC_IE_ON_PER_PKT_IV BIT(11) #define ROC_IE_ON_INB_RPTR_HDR 0x8 enum { @@ -102,6 +101,35 @@ struct roc_ie_on_ip_template { }; }; +union roc_on_ipsec_outb_param1 { + uint16_t u16; + struct { + uint16_t frag_num : 4; + uint16_t rsvd_4_6 : 3; + uint16_t gre_select : 1; + uint16_t dsiv : 1; + uint16_t ikev2 : 1; + uint16_t min_frag_size : 1; + uint16_t per_pkt_iv : 1; + uint16_t tfc_pad_enable : 1; + uint16_t tfc_dummy_pkt : 1; + uint16_t rfc_or_override_mode : 1; + uint16_t custom_hdr_or_p99 : 1; + } s; +}; + +union roc_on_ipsec_inb_param2 { + uint16_t u16; + struct { + uint16_t rsvd_0_10 : 11; + uint16_t gre_select : 1; + uint16_t ikev2 : 1; + uint16_t udp_cksum : 1; + uint16_t ctx_addr_sel : 1; + uint16_t custom_hdr_or_p99 : 1; + } s; +}; + struct roc_ie_on_sa_ctl { uint64_t spi : 32; uint64_t exp_proto_inter_frag : 8; diff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c index a81130b..6455ef9 100644 --- a/drivers/crypto/cnxk/cn9k_ipsec.c +++ b/drivers/crypto/cnxk/cn9k_ipsec.c @@ -280,6 +280,7 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp, struct rte_crypto_sym_xform *auth_xform = crypto_xform->next; struct roc_ie_on_ip_template *template = NULL; struct roc_cpt *roc_cpt = qp->lf.roc_cpt; + union roc_on_ipsec_outb_param1 param1; struct cnxk_cpt_inst_tmpl *inst_tmpl; struct roc_ie_on_outb_sa *out_sa; struct cn9k_sec_session *sess; @@ -407,8 +408,12 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp, w4.u64 = 0; w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_PROCESS_OUTBOUND_IPSEC; w4.s.opcode_minor = ctx_len >> 3; - w4.s.param1 = BIT(9); - w4.s.param1 |= ROC_IE_ON_PER_PKT_IV; + + param1.u16 = 0; + param1.s.ikev2 = 1; + param1.s.per_pkt_iv = 1; + w4.s.param1 = param1.u16; + inst_tmpl->w4 = w4.u64; w7.u64 = 0; @@ -428,6 +433,7 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp, { struct rte_crypto_sym_xform *auth_xform = crypto_xform; struct roc_cpt *roc_cpt = qp->lf.roc_cpt; + union roc_on_ipsec_inb_param2 param2; struct cnxk_cpt_inst_tmpl *inst_tmpl; struct roc_ie_on_inb_sa *in_sa; struct cn9k_sec_session *sess; @@ -478,7 +484,11 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp, w4.u64 = 0; w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC; w4.s.opcode_minor = ctx_len >> 3; - w4.s.param2 = BIT(12); + + param2.u16 = 0; + param2.s.ikev2 = 1; + w4.s.param2 = param2.u16; + inst_tmpl->w4 = w4.u64; w7.u64 = 0; -- 2.7.4