From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70A1BA0032; Thu, 16 Dec 2021 18:54:49 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9465A40DFD; Thu, 16 Dec 2021 18:54:31 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 6244740DF7 for ; Thu, 16 Dec 2021 18:54:29 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BGEr3uU007120 for ; Thu, 16 Dec 2021 09:54:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5mXBGpM/SqSaS0OV2vDZCGoqWddxjFjKKQpPwY6KPks=; b=iwLxWtvrzRdYS1UqzbhR2zaJBOBwzQyc/CE9e7wJdBTZbUGTreENkl1SNgEQ2/+3zGL4 C+lDl5ZD2VXJD6j+6ya+eY7a/gx8zSzIdGNtCQb6dsMPFtRxPBCp1xxYoUdQATLecqnN ABSQoVGkVzZei0P8ndmTMdfoHFP8MyjsHq7tU5z720k7uyujNlnBJ8+do4vE9QJlQN5o 83QeNcRxx0+4j5Uwsz2dvFDTb8cU1h+WsR0TGQHgLrFLE4jUClGwR9DxvCsnyHK2kMbR i3JPTTCS7j7pswK5/n82Kcmvw/b35WXCnhVP5X5XAaBmlF6NeTi0TvP23FDaXm0RQijc kw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3d02p0af28-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Dec 2021 09:54:28 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 16 Dec 2021 09:54:26 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Dec 2021 09:54:26 -0800 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 631E43F7048; Thu, 16 Dec 2021 09:54:24 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Anoob Joseph , Archana Muniganti , Tejasree Kondoj , Subject: [PATCH v2 21/29] crypto/cnxk: add more info on command timeout Date: Thu, 16 Dec 2021 23:19:27 +0530 Message-ID: <1639676975-1316-22-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1639676975-1316-1-git-send-email-anoobj@marvell.com> References: <1638859858-734-1-git-send-email-anoobj@marvell.com> <1639676975-1316-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: NSsrQtCsU29XpHkbY76EOs4oigLCftm5 X-Proofpoint-ORIG-GUID: NSsrQtCsU29XpHkbY76EOs4oigLCftm5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-16_06,2021-12-16_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Print more info when command timeout happens. Print software and hardware queue information. Signed-off-by: Anoob Joseph Signed-off-by: Tejasree Kondoj --- drivers/common/cnxk/hw/cpt.h | 11 ++++++++ drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 1 + drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 1 + drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 43 +++++++++++++++++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 1 + 5 files changed, 57 insertions(+) diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h index 412dd76..4d9c896 100644 --- a/drivers/common/cnxk/hw/cpt.h +++ b/drivers/common/cnxk/hw/cpt.h @@ -91,6 +91,17 @@ union cpt_lf_inprog { } s; }; +union cpt_lf_q_inst_ptr { + uint64_t u; + struct cpt_lf_q_inst_ptr_s { + uint64_t dq_ptr : 20; + uint64_t reserved_20_31 : 12; + uint64_t nq_ptr : 20; + uint64_t reserved_52_62 : 11; + uint64_t xq_xor : 1; + } s; +}; + union cpt_lf_q_base { uint64_t u; struct cpt_lf_q_base_s { diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index f8240e1..1905ea3 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -548,6 +548,7 @@ cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) if (unlikely(rte_get_timer_cycles() > pend_q->time_out)) { plt_err("Request timed out"); + cnxk_cpt_dump_on_err(qp); pend_q->time_out = rte_get_timer_cycles() + DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz(); diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index cf80d47..ac1953b 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -547,6 +547,7 @@ cn9k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) if (unlikely(rte_get_timer_cycles() > pend_q->time_out)) { plt_err("Request timed out"); + cnxk_cpt_dump_on_err(qp); pend_q->time_out = rte_get_timer_cycles() + DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz(); diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index b02f070..f63dcdd 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -703,3 +703,46 @@ cnxk_ae_session_cfg(struct rte_cryptodev *dev, return 0; } + +void +cnxk_cpt_dump_on_err(struct cnxk_cpt_qp *qp) +{ + struct pending_queue *pend_q = &qp->pend_q; + uint64_t inflight, enq_ptr, deq_ptr, insts; + union cpt_lf_q_inst_ptr inst_ptr; + union cpt_lf_inprog lf_inprog; + + plt_print("Lcore ID: %d, LF/QP ID: %d", rte_lcore_id(), qp->lf.lf_id); + plt_print(""); + plt_print("S/w pending queue:"); + plt_print("\tHead: %ld", pend_q->head); + plt_print("\tTail: %ld", pend_q->tail); + plt_print("\tMask: 0x%lx", pend_q->pq_mask); + plt_print("\tInflight count: %ld", + pending_queue_infl_cnt(pend_q->head, pend_q->tail, + pend_q->pq_mask)); + + plt_print(""); + plt_print("H/w pending queue:"); + + lf_inprog.u = plt_read64(qp->lf.rbase + CPT_LF_INPROG); + inflight = lf_inprog.s.inflight; + plt_print("\tInflight in engines: %ld", inflight); + + inst_ptr.u = plt_read64(qp->lf.rbase + CPT_LF_Q_INST_PTR); + + enq_ptr = inst_ptr.s.nq_ptr; + deq_ptr = inst_ptr.s.dq_ptr; + + if (enq_ptr >= deq_ptr) + insts = enq_ptr - deq_ptr; + else + insts = (enq_ptr + pend_q->pq_mask + 1 + 320 + 40) - deq_ptr; + + plt_print("\tNQ ptr: 0x%lx", enq_ptr); + plt_print("\tDQ ptr: 0x%lx", deq_ptr); + plt_print("Insts waiting in CPT: %ld", insts); + + plt_print(""); + roc_cpt_afs_print(qp->lf.roc_cpt); +} diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index 0336ae1..e521f07 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -122,6 +122,7 @@ int cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xform, struct rte_cryptodev_asym_session *sess, struct rte_mempool *pool); +void cnxk_cpt_dump_on_err(struct cnxk_cpt_qp *qp); static inline union rte_event_crypto_metadata * cnxk_event_crypto_mdata_get(struct rte_crypto_op *op) -- 2.7.4