From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 34E68A0032; Thu, 16 Dec 2021 18:55:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A050E4114E; Thu, 16 Dec 2021 18:55:18 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 813A44114E for ; Thu, 16 Dec 2021 18:55:17 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BGBdfPV030228 for ; Thu, 16 Dec 2021 09:55:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=yC+xm1cwcBDz9hInoZb9v6YkkOF48+y1SxfbqxBLcTE=; b=K/doUCHgBGjLNneuzB3QVXnsIaZg199AUsiuvu7QKwVM6GH2yy3G07l26105td7m5K3B GkQ2lRDvaeLGUQ4020dkPZgqi6w7z1Vq9syzv1nvob8q0VqhvrdXjLQ9VdKHFdi+iZzS P5XHm/gZMyR82DURifJdQJUAgtBrcGdz/z/ehYP2jxKVg8/LG07H6TeBbU8CS4jwwhuU KuSpr3E51VdKbNUQXsk/4ClBUxWoRkUposkxmzpzyE8uSjVbJ5nPxZNRqsVq40RhDInN Ii6bY2x+YiUvLV/GoKWLd4Ry2FBr3jL6jVg8//LqVEkQwu5j3mXZ/bPxOnuHuQBPEnz2 fQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3d04s71pc0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Dec 2021 09:55:16 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 16 Dec 2021 09:55:15 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 16 Dec 2021 09:55:15 -0800 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id DFF5B3F707E; Thu, 16 Dec 2021 09:55:12 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Anoob Joseph , Archana Muniganti , Tejasree Kondoj , Subject: [PATCH v2 29/29] crypto/cnxk: update microcode completion handling Date: Thu, 16 Dec 2021 23:19:35 +0530 Message-ID: <1639676975-1316-30-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1639676975-1316-1-git-send-email-anoobj@marvell.com> References: <1638859858-734-1-git-send-email-anoobj@marvell.com> <1639676975-1316-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: vn4B9CW9esYsjMMMRwrUh3TJTy7zkkUX X-Proofpoint-ORIG-GUID: vn4B9CW9esYsjMMMRwrUh3TJTy7zkkUX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-16_06,2021-12-16_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update microcode completion code handling to update the required mbuf & crypto op flags. IP checksum good case is now reported by specific microcode completion code. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 59 ++++++++++--------------------- drivers/crypto/cnxk/cn10k_ipsec.c | 1 - drivers/crypto/cnxk/cn10k_ipsec.h | 1 - 3 files changed, 18 insertions(+), 43 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 1905ea3..d217bbf 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -50,8 +50,7 @@ cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op) static __rte_always_inline int __rte_hot cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, - struct cn10k_sec_session *sess, - struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst) + struct cn10k_sec_session *sess, struct cpt_inst_s *inst) { struct rte_crypto_sym_op *sym_op = op->sym; struct cn10k_ipsec_sa *sa; @@ -71,10 +70,8 @@ cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, if (sa->is_outbound) ret = process_outb_sa(&qp->lf, op, sa, inst); - else { - infl_req->op_flags |= CPT_OP_FLAGS_IPSEC_DIR_INBOUND; + else ret = process_inb_sa(op, sa, inst); - } return ret; } @@ -127,8 +124,7 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) { sec_sess = get_sec_session_private_data( sym_op->sec_session); - ret = cpt_sec_inst_fill(qp, op, sec_sess, infl_req, - &inst[0]); + ret = cpt_sec_inst_fill(qp, op, sec_sess, &inst[0]); if (unlikely(ret)) return 0; w7 = sec_sess->sa.inst.w7; @@ -346,52 +342,34 @@ static inline void cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res) { - struct rte_mbuf *m = cop->sym->m_src; + struct rte_mbuf *mbuf = cop->sym->m_src; const uint16_t m_len = res->rlen; - m->data_len = m_len; - m->pkt_len = m_len; -} - -static inline void -cn10k_cpt_sec_ucc_process(struct rte_crypto_op *cop, - struct cpt_inflight_req *infl_req, - const uint8_t uc_compcode) -{ - struct cn10k_sec_session *sess; - struct cn10k_ipsec_sa *sa; - struct rte_mbuf *mbuf; - - if (uc_compcode == ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST) - cop->aux_flags = RTE_CRYPTO_OP_AUX_FLAGS_IPSEC_SOFT_EXPIRY; - - if (!(infl_req->op_flags & CPT_OP_FLAGS_IPSEC_DIR_INBOUND)) - return; - - sess = get_sec_session_private_data(cop->sym->sec_session); - sa = &sess->sa; + mbuf->data_len = m_len; + mbuf->pkt_len = m_len; - mbuf = cop->sym->m_src; - - switch (uc_compcode) { + switch (res->uc_compcode) { case ROC_IE_OT_UCC_SUCCESS: - if (sa->ip_csum_enable) - mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; break; case ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM: mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD; break; case ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM: - mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; - if (sa->ip_csum_enable) - mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; + mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD | + RTE_MBUF_F_RX_IP_CKSUM_GOOD; break; case ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM: - mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD; - if (sa->ip_csum_enable) - mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; + mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD | + RTE_MBUF_F_RX_IP_CKSUM_GOOD; + break; + case ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM: + mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; + break; + case ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST: + cop->aux_flags = RTE_CRYPTO_OP_AUX_FLAGS_IPSEC_SOFT_EXPIRY; break; default: + plt_dp_err("Success with unknown microcode completion code"); break; } } @@ -412,7 +390,6 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) { if (likely(compcode == CPT_COMP_WARN)) { /* Success with additional info */ - cn10k_cpt_sec_ucc_process(cop, infl_req, uc_compcode); cn10k_cpt_sec_post_process(cop, res); } else { cop->status = RTE_CRYPTO_OP_STATUS_ERROR; diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c index a93c211..7f4ccaf 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.c +++ b/drivers/crypto/cnxk/cn10k_ipsec.c @@ -201,7 +201,6 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf, if (ipsec_xfrm->options.ip_csum_enable) { param1.s.ip_csum_disable = ROC_IE_OT_SA_INNER_PKT_IP_CSUM_ENABLE; - sa->ip_csum_enable = true; } /* Disable L4 checksum verification by default */ diff --git a/drivers/crypto/cnxk/cn10k_ipsec.h b/drivers/crypto/cnxk/cn10k_ipsec.h index cc7ca19..647a71c 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.h +++ b/drivers/crypto/cnxk/cn10k_ipsec.h @@ -19,7 +19,6 @@ struct cn10k_ipsec_sa { uint16_t max_extended_len; uint16_t iv_offset; uint8_t iv_length; - bool ip_csum_enable; bool is_outbound; /** -- 2.7.4