From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 212F0A04A4; Wed, 2 Mar 2022 16:12:40 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9CF2942715; Wed, 2 Mar 2022 16:12:39 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 4DF1040141 for ; Wed, 2 Mar 2022 16:12:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646233958; x=1677769958; h=from:to:cc:subject:date:message-id; bh=ywt/cGBGLqyZAhj5qn3vdUTMW3TQNuF3cAJNPZUwlT8=; b=GTULtQNF7D/6/jZj0xI4fkdiavbGW6U5N0iCRgFzatrPpE1jHpmmbqMJ YMUGdNjazliZ/nScXBr5/+UPneylMWUFM0+tbEKbPXmaMIBhUpAkbvB/J aHHMOFdzUGLfYyNKnbrn9OYLnMyg6ZP1Qy8NghIRxYDrVgZ5AY9WnNLrJ vBRwB65+VjRPuQEVSb8CuHfsTelUCn/GOq6FUsu4kI3v362RcZym28m/E 2zdKY1qyPDiIGr/wUHhPTMyUdzYMbgSM5RDaMmEF6wU+VL0utkYGcCHil ZSGIGfiX8n/FziFuiurhcvwP0Qd9fKXXFcDgE3dOVFbsPO5nQ0uCEsPih A==; X-IronPort-AV: E=McAfee;i="6200,9189,10274"; a="339850714" X-IronPort-AV: E=Sophos;i="5.90,149,1643702400"; d="scan'208";a="339850714" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 07:12:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,149,1643702400"; d="scan'208";a="551284910" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by orsmga008.jf.intel.com with ESMTP; 02 Mar 2022 07:12:12 -0800 From: Timothy McDaniel To: jerinj@marvell.com Cc: john.mcnamara@intel.com, dev@dpdk.org Subject: [PATCH] event/dlb2: fix invalid shift value Date: Wed, 2 Mar 2022 09:12:08 -0600 Message-Id: <1646233928-4124603-1-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a check to ensure that all shift counts are valid. Shifting by more than 63 bits may result in undefined behavior, as noted during coverity scan. Fixes: e697f35dbdd1 ("event/dlb2: update rolling mask used for dequeue") Coverity issue: 376527 Signed-off-by: Timothy McDaniel --- drivers/event/dlb2/dlb2.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 09abdd1660..7789dd74e0 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -3916,15 +3916,17 @@ dlb2_hw_dequeue_sparse(struct dlb2_eventdev *dlb2, &events[num], &qes[0], num_avail); - num += n_iter; - /* update rolling_mask for vector code support */ - m_rshift = qm_port->cq_rolling_mask >> n_iter; - m_lshift = qm_port->cq_rolling_mask << (64 - n_iter); - m2_rshift = qm_port->cq_rolling_mask_2 >> n_iter; - m2_lshift = qm_port->cq_rolling_mask_2 << + if (n_iter != 0) { + num += n_iter; + /* update rolling_mask for vector code support */ + m_rshift = qm_port->cq_rolling_mask >> n_iter; + m_lshift = qm_port->cq_rolling_mask << (64 - n_iter); + m2_rshift = qm_port->cq_rolling_mask_2 >> n_iter; + m2_lshift = qm_port->cq_rolling_mask_2 << (64 - n_iter); - qm_port->cq_rolling_mask = (m_rshift | m2_lshift); - qm_port->cq_rolling_mask_2 = (m2_rshift | m_lshift); + qm_port->cq_rolling_mask = (m_rshift | m2_lshift); + qm_port->cq_rolling_mask_2 = (m2_rshift | m_lshift); + } } else { /* !use_scalar */ num_avail = dlb2_recv_qe_sparse_vec(qm_port, &events[num], -- 2.25.1