From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B02B8A00BE; Mon, 25 Apr 2022 07:39:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D3312427FB; Mon, 25 Apr 2022 07:39:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 47B0642809 for ; Mon, 25 Apr 2022 07:39:32 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23OMoWks011219 for ; Sun, 24 Apr 2022 22:39:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kPYlc318d0Hx+/Ozwi4ny//GXnJh9ZYemxPr2Z8XyDI=; b=Whe0Dqu5JCvU1oFNtEtgyJGfd+ENMe4pEQKT5S5nqpqYyG+Ae9xfySHo7Mpk/XewPe6a 0PKm/UvEQX9YJ++Ow950rC6Gw1YZjkBcZW7hYde+bpLV7TvAlsM+Ums/kQ8uDBlwGjE7 weEvvyM5MnDD558A+h/TmYrZG6Xzj2RYEZdMcSk1vjR5f9M3Ox55WXKW8WAnUvTZTMlo oLf3gJCHQ00+82M88XhWElz5cWYo1fd/B91XxnQQ9P4+m+nlfGywXBZGS5s/j91ZHhHz QFADYfHar5sTJ0Xi8tI9HGpfMdZ4t6RiIgWp+9dT1/p4S1Qh/T1T4ZmRs5+N9fhlc9Q0 KA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fmgymcb10-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 24 Apr 2022 22:39:31 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 24 Apr 2022 22:39:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 24 Apr 2022 22:39:29 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.69.240]) by maili.marvell.com (Postfix) with ESMTP id 298473F7073; Sun, 24 Apr 2022 22:39:26 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Anoob Joseph , Archana Muniganti , Tejasree Kondoj , Subject: [PATCH 4/5] common/cnxk: add timeout for ctx write operation Date: Mon, 25 Apr 2022 11:08:24 +0530 Message-ID: <1650865105-66-5-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1650865105-66-1-git-send-email-anoobj@marvell.com> References: <1650865105-66-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: iJGnR3hGMoJnD4T6h_yKJmanqUTKfIqF X-Proofpoint-ORIG-GUID: iJGnR3hGMoJnD4T6h_yKJmanqUTKfIqF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-25_01,2022-04-22_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add busy wait and polling for ctx write operation rather than waiting with 1 ms delay. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_cpt.c | 31 +++++++++++++++++++++---------- drivers/common/cnxk/roc_platform.h | 7 ++++--- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index b3a3649..742723a 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -915,9 +915,9 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, uint16_t sa_len) { uintptr_t lmt_base = lf->lmt_base; + union cpt_res_s res, *hw_res; uint64_t lmt_arg, io_addr; struct cpt_inst_s *inst; - union cpt_res_s *res; uint16_t lmt_id; uint64_t *dptr; int i; @@ -927,8 +927,8 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, memset(inst, 0, sizeof(struct cpt_inst_s)); - res = plt_zmalloc(sizeof(*res), ROC_CPT_RES_ALIGN); - if (res == NULL) { + hw_res = plt_zmalloc(sizeof(*hw_res), ROC_CPT_RES_ALIGN); + if (hw_res == NULL) { plt_err("Couldn't allocate memory for result address"); return -ENOMEM; } @@ -936,7 +936,7 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, dptr = plt_zmalloc(sa_len, 8); if (dptr == NULL) { plt_err("Couldn't allocate memory for SA dptr"); - plt_free(res); + plt_free(hw_res); return -ENOMEM; } @@ -944,8 +944,8 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, dptr[i] = plt_cpu_to_be_64(((uint64_t *)sa_dptr)[i]); /* Fill CPT_INST_S for WRITE_SA microcode op */ - res->cn10k.compcode = CPT_COMP_NOT_DONE; - inst->res_addr = (uint64_t)res; + hw_res->cn10k.compcode = CPT_COMP_NOT_DONE; + inst->res_addr = (uint64_t)hw_res; inst->dptr = (uint64_t)dptr; inst->w4.s.param2 = sa_len >> 3; inst->w4.s.dlen = sa_len; @@ -959,14 +959,25 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, io_addr = lf->io_addr | ROC_CN10K_CPT_INST_DW_M1 << 4; roc_lmt_submit_steorl(lmt_arg, io_addr); - plt_wmb(); + plt_io_wmb(); + + /* Use 1 min timeout for the poll */ + const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz(); /* Wait until CPT instruction completes */ - while (res->cn10k.compcode == CPT_COMP_NOT_DONE) - plt_delay_ms(1); + do { + res.u64[0] = __atomic_load_n(&hw_res->u64[0], __ATOMIC_RELAXED); + if (unlikely(plt_tsc_cycles() > timeout)) + break; + } while (res.cn10k.compcode == CPT_COMP_NOT_DONE); - plt_free(res); plt_free(dptr); + plt_free(hw_res); + + if (res.cn10k.compcode != CPT_COMP_WARN) { + plt_err("Write SA operation timed out"); + return -ETIMEDOUT; + } return 0; } diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 28004b1..86987ae 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -184,9 +184,10 @@ #define plt_memzone_reserve_aligned(name, len, flags, align) \ rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) -#define plt_tsc_hz rte_get_tsc_hz -#define plt_delay_ms rte_delay_ms -#define plt_delay_us rte_delay_us +#define plt_tsc_hz rte_get_tsc_hz +#define plt_tsc_cycles rte_get_tsc_cycles +#define plt_delay_ms rte_delay_ms +#define plt_delay_us rte_delay_us #define plt_lcore_id rte_lcore_id -- 2.7.4