From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D92E4A00BE; Mon, 25 Apr 2022 07:40:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8DDC34280C; Mon, 25 Apr 2022 07:39:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 183054280F for ; Mon, 25 Apr 2022 07:39:35 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23ON1FwA009631 for ; Sun, 24 Apr 2022 22:39:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vlX8YSzRaY0ln6k3w4F6zBuVYIn05xBihNeUfJFTxLQ=; b=eluSkbXwvbAw8Bo14vg4dyBq39jm+Bt9FxPmaMCLTT28juEfEfFusQ94pKynLAZeExV0 A1TOtX34uhIpR1TgNzN2i533E+JraJUdIC+gumMoe0B8dFaqBjFMWe5IKQgZlhcC2JuR tm5hAZ6IgbPIGuZBOD2gYAg8AkgJZ86K5WXfxhVIe0YmjBhogWOUkIc3p2y/xc+aLtF8 OX5Nz84IFs/bm4kDzPt48qfAkq8XqtjjD9bF0Dl3Ei7tZBM28JGNu0Wkz5GfXSSJPYHS Q7rXIzfdgjS2d4RYdOzQCaCwi+VhP/9raJrrsHsSBHkMW3lCj1dX+Kx++9WqBUbx5ACs WA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fmetqmhy2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 24 Apr 2022 22:39:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 24 Apr 2022 22:39:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 24 Apr 2022 22:39:33 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.69.240]) by maili.marvell.com (Postfix) with ESMTP id 63FFD3F7073; Sun, 24 Apr 2022 22:39:31 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Anoob Joseph , Archana Muniganti , Tejasree Kondoj , Subject: [PATCH 5/5] crypto/cnxk: use set ctx operation for session destroy Date: Mon, 25 Apr 2022 11:08:25 +0530 Message-ID: <1650865105-66-6-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1650865105-66-1-git-send-email-anoobj@marvell.com> References: <1650865105-66-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: A-UahNsaroVJKYogtaEs_7C7VnTIjzGX X-Proofpoint-GUID: A-UahNsaroVJKYogtaEs_7C7VnTIjzGX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-25_01,2022-04-22_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Usage of flush and invalidate would involve delays to account for flush delay. Use set_ctx operation instead. When set_ctx fails, fall back to flush + invalidate scheme. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cn10k_ipsec.c | 44 ++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c index 3a2bf0f..d6ff134 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec.c +++ b/drivers/crypto/cnxk/cn10k_ipsec.c @@ -333,6 +333,8 @@ cn10k_sec_session_destroy(void *dev, struct rte_security_session *sec_sess) struct cn10k_ipsec_sa *sa; struct cnxk_cpt_qp *qp; struct roc_cpt_lf *lf; + void *sa_dptr = NULL; + int ret; sess = get_sec_session_private_data(sec_sess); if (sess == NULL) @@ -349,16 +351,44 @@ cn10k_sec_session_destroy(void *dev, struct rte_security_session *sec_sess) /* Trigger CTX flush to write dirty data back to DRAM */ roc_cpt_lf_ctx_flush(lf, &sa->in_sa, false); - /* Wait for 1 ms so that flush is complete */ - rte_delay_ms(1); + ret = -1; - w2 = (union roc_ot_ipsec_sa_word2 *)&sa->in_sa.w2; - w2->s.valid = 0; + if (sa->is_outbound) { + sa_dptr = plt_zmalloc(sizeof(struct roc_ot_ipsec_outb_sa), 8); + if (sa_dptr != NULL) { + roc_ot_ipsec_outb_sa_init(sa_dptr); - plt_atomic_thread_fence(__ATOMIC_SEQ_CST); + ret = roc_cpt_ctx_write( + lf, sa_dptr, &sa->out_sa, + sizeof(struct roc_ot_ipsec_outb_sa)); + } + } else { + sa_dptr = plt_zmalloc(sizeof(struct roc_ot_ipsec_inb_sa), 8); + if (sa_dptr != NULL) { + roc_ot_ipsec_inb_sa_init(sa_dptr, false); + + ret = roc_cpt_ctx_write( + lf, sa_dptr, &sa->in_sa, + sizeof(struct roc_ot_ipsec_inb_sa)); + } + } - /* Trigger CTX reload to fetch new data from DRAM */ - roc_cpt_lf_ctx_reload(lf, &sa->in_sa); + plt_free(sa_dptr); + + if (ret) { + /* MC write_ctx failed. Attempt reload of CTX */ + + /* Wait for 1 ms so that flush is complete */ + rte_delay_ms(1); + + w2 = (union roc_ot_ipsec_sa_word2 *)&sa->in_sa.w2; + w2->s.valid = 0; + + plt_atomic_thread_fence(__ATOMIC_SEQ_CST); + + /* Trigger CTX reload to fetch new data from DRAM */ + roc_cpt_lf_ctx_reload(lf, &sa->in_sa); + } sess_mp = rte_mempool_from_obj(sess); -- 2.7.4