From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
	by inbox.dpdk.org (Postfix) with ESMTP id C9DE6A04FD;
	Mon, 23 May 2022 12:23:39 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
	by mails.dpdk.org (Postfix) with ESMTP id CD17342B84;
	Mon, 23 May 2022 12:23:01 +0200 (CEST)
Received: from mga18.intel.com (mga18.intel.com [134.134.136.126])
 by mails.dpdk.org (Postfix) with ESMTP id D479742B8E
 for <dev@dpdk.org>; Mon, 23 May 2022 12:22:59 +0200 (CEST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;
 d=intel.com; i=@intel.com; q=dns/txt; s=Intel;
 t=1653301380; x=1684837380;
 h=from:to:cc:subject:date:message-id:in-reply-to: references;
 bh=mnOOi7xfkNfV0i8YQK29UQMF9j86DxaWww6eJr5tNhs=;
 b=YHM3tiRU7CcIMxJCwA5DXAu4ibbVcM+Klz3nKo5MTFW4odaYStldXVzL
 Zqi79d1V+YPJrEZs67HK4Njyld5+JGbjhM3iP0ks3gk2KeH/QWko5HRGG
 dPWCXL/CV/DblwWvCQbGWiDGofcKi9Nr8dPfvmGxPaiyi9yStYw4Hp4it
 So9w59NnQFY6ef8aM6PEQqi3viEEC+suQdtwphif6Laz11x77NZ8GO+Xr
 T70TLil9pZ9Sek7YxM/e+LFgHYqVNawkuCbC9RDrUV8Zz5oWAQqFsBzS9
 XaY0ZDot7+bweDEqZW4TJZD8BMA1Rvxcp8t4XEjEIwMKwbYpGRHU8a4hD w==;
X-IronPort-AV: E=McAfee;i="6400,9594,10355"; a="255239395"
X-IronPort-AV: E=Sophos;i="5.91,246,1647327600"; d="scan'208";a="255239395"
Received: from orsmga006.jf.intel.com ([10.7.209.51])
 by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
 23 May 2022 03:22:59 -0700
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.91,246,1647327600"; d="scan'208";a="547889520"
Received: from dpdk-dipei.sh.intel.com ([10.67.110.238])
 by orsmga006.jf.intel.com with ESMTP; 23 May 2022 03:22:57 -0700
From: Andy Pei <andy.pei@intel.com>
To: dev@dpdk.org
Cc: chenbo.xia@intel.com, maxime.coquelin@redhat.com, gang.cao@intel.com,
 changpeng.liu@intel.com, rosen.xu@intel.com, qimaix.xiao@intel.com
Subject: [PATCH v9 11/13] vdpa/ifc: add log for config space of virtio blk
Date: Mon, 23 May 2022 17:35:22 +0800
Message-Id: <1653298524-232138-12-git-send-email-andy.pei@intel.com>
X-Mailer: git-send-email 1.8.3.1
In-Reply-To: <1653298524-232138-1-git-send-email-andy.pei@intel.com>
References: <1643093258-47258-2-git-send-email-andy.pei@intel.com>
 <1653298524-232138-1-git-send-email-andy.pei@intel.com>
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org

Add some log of virtio blk device config space information
at VDPA launch before qemu connects.

Signed-off-by: Andy Pei <andy.pei@intel.com>
---
 drivers/vdpa/ifc/ifcvf_vdpa.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/vdpa/ifc/ifcvf_vdpa.c b/drivers/vdpa/ifc/ifcvf_vdpa.c
index 1c5746a..80d6261 100644
--- a/drivers/vdpa/ifc/ifcvf_vdpa.c
+++ b/drivers/vdpa/ifc/ifcvf_vdpa.c
@@ -1382,6 +1382,9 @@ struct rte_vdpa_dev_info dev_info[] = {
 	struct rte_kvargs *kvlist = NULL;
 	int ret = 0;
 	int16_t device_id;
+	uint64_t capacity = 0;
+	uint8_t *byte;
+	uint32_t i;
 
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 		return 0;
@@ -1448,6 +1451,37 @@ struct rte_vdpa_dev_info dev_info[] = {
 		internal->features = features &
 					~(1ULL << VIRTIO_F_IOMMU_PLATFORM);
 		internal->features |= dev_info[IFCVF_BLK].features;
+
+		/* cannot read 64-bit register in one attempt,
+		 * so read byte by byte.
+		 */
+		for (i = 0; i < sizeof(internal->hw.blk_cfg->capacity); i++) {
+			byte = (uint8_t *)&internal->hw.blk_cfg->capacity + i;
+			capacity |= (uint64_t)*byte << (i * 8);
+		}
+		/* The capacity is number of sectors in 512-byte.
+		 * So right shift 1 bit  we get in K,
+		 * another right shift 10 bits we get in M,
+		 * right shift 10 more bits, we get in G.
+		 * To show capacity in G, we right shift 21 bits in total.
+		 */
+		DRV_LOG(DEBUG, "capacity  : %"PRIu64"G", capacity >> 21);
+
+		DRV_LOG(DEBUG, "size_max  : 0x%08x",
+			internal->hw.blk_cfg->size_max);
+		DRV_LOG(DEBUG, "seg_max   : 0x%08x",
+			internal->hw.blk_cfg->seg_max);
+		DRV_LOG(DEBUG, "blk_size  : 0x%08x",
+			internal->hw.blk_cfg->blk_size);
+		DRV_LOG(DEBUG, "geometry");
+		DRV_LOG(DEBUG, "    cylinders: %u",
+			internal->hw.blk_cfg->geometry.cylinders);
+		DRV_LOG(DEBUG, "    heads    : %u",
+			internal->hw.blk_cfg->geometry.heads);
+		DRV_LOG(DEBUG, "    sectors  : %u",
+			internal->hw.blk_cfg->geometry.sectors);
+		DRV_LOG(DEBUG, "num_queues: 0x%08x",
+			internal->hw.blk_cfg->num_queues);
 	}
 
 	list->internal = internal;
-- 
1.8.3.1